SPI bus voltage level issue - MISO


Hi, I’m seeing an issue with MISO high voltage. The MISO is measured at 1.45V (1.8V is the intended design). The MISO is connected to a level translator that translates 3.3V to 1.8V. The MISO on the 3.3V side shows the correct waveform. And all other SPI lines are correct at 1.8V. What can be causing this pull down by Jetson during the active state?

The scope capture shows the 1.45V abnormal waveform (top) and the 3.3V side of the level translator (bottom).

Hi, please read the 40-pin header docs first. There are some requests on the pins design of the header.


Hi Trumany, thanks for the doc. My connection to the 40pin header is correct since I have the correct SPI communication. The concern is not about the functionality. It’s a voltage margin issue where 1.45V is closed to the logic1 minimum voltage requirement. I’m using TXB0108 as level translator between my MCU (3.3V) and Jetson (1.8V). I’m connecting to Jetson’s SPI0 SPI interface. Should I be using SPI1 interface? Also Is TXB0108 the recommended part for level translation with Jetson?

Here’s SCH of my SPI to Jetson’s 40pin connector:

From the scope capture, it looks like there’s an internal pull-down at Jetson’s MISO (pin93). Can you confirm if that’s the case? Here’s the scope capture with the issue highlighted:

Pin 93 pass thru the level shift, please refer to the datasheet of TXB0108 for its pull-up/down setting.

Theres’ no internal pull-up/down for TXB0108.

In addition to the pull-down behavior, another question is why it pulls to 1.4V? TXB0108 has a 4kohm output resistance so Jetson has a 14kohm pull down at the MISO pin. I was able to confirm the 14kohm pull-down with a measurement. Is this expected? Can you share the SW setting to fix this?

TXB0108 has load requests as said in docs, not relate to Jetson pin. Please read the datasheet of TXB0108 and the 40-pin header carefully.