Spi3 connect nor flash

cat /etc/nv_tegra_release

R32 (release), REVISION: 6.1, GCID: 27863751, BOARD: t186ref, EABI: aarch64, DATE: Mon Jul 26 19:36:31 UTC 2021

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##SPI3
pinmux.0x0243d048 = 0x00000415; # spi3_sck_py0: rsvd1, pull-down, tristate-enable, input-disable, io_high_voltage-disable, lpdr-disable
pinmux.0x0243d008 = 0x00000001; # spi3_miso_py1: rsvd1, tristate-disable, input-disable, io_high_voltage-disable, lpdr-disable
pinmux.0x0243d060 = 0x00000411; # spi3_mosi_py2: rsvd1, tristate-enable, input-disable, io_high_voltage-disable, lpdr-disable
pinmux.0x0243d018 = 0x00000415; # spi3_cs0_py3: rsvd1, pull-down, tristate-enable, input-disable, io_high_voltage-disable, lpdr-disable
pinmux.0x0243d028 = 0x00000001; # spi3_cs1_py4: rsvd1, tristate-disable, input-disable, io_high_voltage-disable, lpdr-disable

spi@3230000 {
	status = "okay";
	spi@2 {
		compatible = "tegra-spidev";
		reg = <0x0>;
		spi-max-frequency = <33000000>;
		controller-data {
			nvidia,enable-hw-based-cs;
			nvidia,rx-clk-tap-delay = <0x11>;
		};

		spi-flash@0 {
			compatible = "m25p80";
			reg = <0>;
			spi-max-frequency = <20000000>;
		};

	};

};

tegra194-p2888-0001-p2822-0000.dts (368.4 KB)

root@user-desktop:/home/user# ./spidev_test -D /dev/spidev2.0 -v
spi mode: 0x0
bits per word: 8
max speed: 500000 Hz (500 KHz)
TX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D | …@…?
RX | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | …

  1. How to use spidev_test to test whether SPI BUS is normal ?

  2. my nor flash is “mt25qu01g” … But the kernel does not have this device,
    May I have any suggestions so that I can use this nor flash ?

It seems to be supported in kerenl 5.15
https://github.com/torvalds/linux/commit/15f5c7e54e658aa56e815192cfca59a8b4c6a439#diff-ef8ada8e73ecfd91e078b10cba3b89f3647f1ba03c5d36b24592e5ea99189042

The SPI pin configure should be like below.

Bank: 0 Reg: 0x0243d010 Val: 0x00000448 -> spi1_cs0_pz6
Bank: 0 Reg: 0x0243d020 Val: 0x00000444 -> spi1_miso_pz4
Bank: 0 Reg: 0x0243d040 Val: 0x00000444 -> spi1_sck_pz3
Bank: 0 Reg: 0x0243d050 Val: 0x00000448 -> spi1_cs1_pz7
Bank: 0 Reg: 0x0243d058 Val: 0x00000444 -> spi1_mosi_pz5
Bank: 0 Reg: 0x0243d008 Val: 0x00000444 -> spi3_miso_py1
Bank: 0 Reg: 0x0243d018 Val: 0x00000448 -> spi3_cs0_py3
Bank: 0 Reg: 0x0243d028 Val: 0x00000448 -> spi3_cs1_py4
Bank: 0 Reg: 0x0243d048 Val: 0x00000444 -> spi3_sck_py0
Bank: 0 Reg: 0x0243d060 Val: 0x00000444 -> spi3_mosi_py2

After the modification, execute the command, but still cannot measure the signals such as spi3_sck_py0

./spidev_test -D /dev/spidev2.0 -v
spi mode: 0x0
bits per word: 8
max speed: 500000 Hz (500 KHz)
TX | FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF F0 0D | …@…?
RX | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | …

Could you connect SPI like below

  1. Connect the device loopback as spi1 MISO <-> spi3 MISO / spi1 MOSI <-> spi3 MOSI / spi1 SCK<-> spi3 SCK / spi1 CS0 <-> spi CS0

  2. Run below script.
    sudo ./spidev_test -D /dev/spidev2.0 -s8000000 -g512 -b32 -H -p0 -n1 -r &
    sleep 5
    sudo ./spidev_test -D /dev/spidev0.0 -s8000000 -g512 -b32 -H -p0 -n1 -zzz -t

2 -b32 -H -p0 -n1 -r me/user# ./spidev_test_nv -D /dev/spidev2.0 -s8000000 -g512
/dev/spidev2.0: TEST FAILED !!! (status:-1)

???
Has not been modified to a loopback circuit
Is it wrong to execute directly?

Please connect as comment for loopback test.

Can it be changed to spi2 <-> spi3?

Have a check this pin map,
The pin 19,21,23,24, 26 is the spi0 aka spidev0.x and pin 13,16,18, 22, 37 is spi2 aka spidev2.x

Because of circuit problems
Can I use spi2 and spi3 to test each other?
How to set up spi2

spi@c260000 {
status = “okay”;
spi@0 { /* chip select 0 */
compatible = “tegra-spidev”;
reg = <0x0>;
spi-max-frequency = <50000000>;
controller-data {
nvidia,enable-hw-based-cs;
nvidia,rx-clk-tap-delay = <0x10>;
nvidia,tx-clk-tap-delay = <0x0>;
};
};
};

I can see /dev/spidev1.0

Does NX have spi2 pin out?

My board spi2 has test points

image

Why MISO to MISO ?
spi2 MISO <-> spi3 MISO /
spi2 MOSI <-> spi3 MOSI /
spi2 SCK<-> spi3 SCK /
spi2 CS0 <-> spi3 CS0

My bad, should be SPI1_MOSI<- ->SPI3_MOSI, SPI1_MISO<- ->SPI3_MISO, SPI1_CLK<–>SPI3_CLK, SP1_CS0 <–> SPI3_CS0 and SPI1_CS1->SPI3_CS1.

SPI1_MOSI<- ->SPI3_MOSI ???

For your case is SPI2, never mind just connect the MOSI to another MOSI and MISO to MISO for two device(master/slave) loopback test.

An error occurs when executing spidev_test

sudo ./spidev_test_nv -D /dev/spidev2.0 -s8000000 -g512 -b32 -H -p0 -n1 -r &

[1] 8626
root@user-desktop:/home/user# /dev/spidev2.0: TEST FAILED !!! (status:-1)

1112_spi23.log (5.1 KB)

DTS
tegra194-p2888-0001-p2822-0000.dts (368.6 KB)

Looks like the dts didn’t configure the SPI pin like jetson-io do.

 sudo cat /sys/kernel/debug/tegra_pinctrl_reg | grep -i spi
[sudo] password for nvidia:
Bank: 0 Reg: 0x0243d008 Val: 0x00000444 -> spi3_miso_py1
Bank: 0 Reg: 0x0243d010 Val: 0x00000448 -> spi1_cs0_pz6
Bank: 0 Reg: 0x0243d018 Val: 0x00000448 -> spi3_cs0_py3
Bank: 0 Reg: 0x0243d020 Val: 0x00000444 -> spi1_miso_pz4
Bank: 0 Reg: 0x0243d028 Val: 0x00000448 -> spi3_cs1_py4
Bank: 0 Reg: 0x0243d040 Val: 0x00000444 -> spi1_sck_pz3
Bank: 0 Reg: 0x0243d048 Val: 0x00000444 -> spi3_sck_py0
Bank: 0 Reg: 0x0243d050 Val: 0x00000448 -> spi1_cs1_pz7
Bank: 0 Reg: 0x0243d058 Val: 0x00000444 -> spi1_mosi_pz5
Bank: 0 Reg: 0x0243d060 Val: 0x00000444 -> spi3_mosi_py2

spit@user-desktop:/home/user# cat /sys/kernel/debug/tegra_pinctrl_reg | grep -i s
Bank: 1 Reg: 0x0c302028 Val: 0x00000400 → spi2_mosi_pcc2
Bank: 1 Reg: 0x0c302038 Val: 0x00000400 → spi2_cs0_pcc3
Bank: 1 Reg: 0x0c302048 Val: 0x00000400 → spi2_sck_pcc0
Bank: 1 Reg: 0x0c302050 Val: 0x00000450 → spi2_miso_pcc1
Bank: 0 Reg: 0x0243b000 Val: 0x00023440 → qspi0_io3_pc5
Bank: 0 Reg: 0x0243b008 Val: 0x00023440 → qspi0_io2_pc4
Bank: 0 Reg: 0x0243b010 Val: 0x00023440 → qspi0_io1_pc3
Bank: 0 Reg: 0x0243b018 Val: 0x00023440 → qspi0_io0_pc2
Bank: 0 Reg: 0x0243b020 Val: 0x00023460 → qspi0_sck_pc0
Bank: 0 Reg: 0x0243b028 Val: 0x00023400 → qspi0_cs_n_pc1
Bank: 0 Reg: 0x0243b030 Val: 0x00023440 → qspi1_io3_pd3
Bank: 0 Reg: 0x0243b038 Val: 0x00023440 → qspi1_io2_pd2
Bank: 0 Reg: 0x0243b040 Val: 0x00023440 → qspi1_io1_pd1
Bank: 0 Reg: 0x0243b048 Val: 0x00023440 → qspi1_io0_pd0
Bank: 0 Reg: 0x0243b050 Val: 0x00023460 → qspi1_sck_pc6
Bank: 0 Reg: 0x0243b058 Val: 0x00023400 → qspi1_cs_n_pc7
Bank: 0 Reg: 0x0243b060 Val: 0x00002000 → qspi_comp
Bank: 0 Reg: 0x0243d008 Val: 0x00000444 → spi3_miso_py1
Bank: 0 Reg: 0x0243d010 Val: 0x00000448 → spi1_cs0_pz6
Bank: 0 Reg: 0x0243d018 Val: 0x00000448 → spi3_cs0_py3
Bank: 0 Reg: 0x0243d020 Val: 0x00000444 → spi1_miso_pz4
Bank: 0 Reg: 0x0243d028 Val: 0x00000448 → spi3_cs1_py4
Bank: 0 Reg: 0x0243d040 Val: 0x00000444 → spi1_sck_pz3
Bank: 0 Reg: 0x0243d048 Val: 0x00000054 → spi3_sck_py0
Bank: 0 Reg: 0x0243d050 Val: 0x00000448 → spi1_cs1_pz7
Bank: 0 Reg: 0x0243d058 Val: 0x00000444 → spi1_mosi_pz5
Bank: 0 Reg: 0x0243d060 Val: 0x00000444 → spi3_mosi_py2

why ??
Bank: 0 Reg: 0x0243d048 Val: 0x00000054 → spi3_sck_py0

I set
##SPI3
pinmux.0x0243d048 = 0x00000444; #spi3_sck_py0
pinmux.0x0243d008 = 0x00000444; #spi3_miso_py1
pinmux.0x0243d060 = 0x00000444; #spi3_mosi_py2
pinmux.0x0243d018 = 0x00000448; #spi3_cs0_py3
pinmux.0x0243d028 = 0x00000448; #spi3_cs1_py4

tegra19x-mb1-pinmux-p2888-0000-a04-p2822-0000-b01.cfg (30.4 KB)

It’s could be device tree over write it.

I can’t find which side of dts to change to the setting of spi3_sck_py0

https://forums.developer.nvidia.com/uploads/short-url/bB2E4qSk1DyD5eGgF4offxV04uU.dts

Should modify tegra19x-mb1-pinmux-p3668-a01.cfg for Xavier NX platform.