I was looking through the Jetson Xavier NX devkit schematics and found that the NVMe M.2 connector SUSCLK signal is connected to a Clock chip.
There is a SLEEP/SUSPEND CLK signal on Jetson Xavier NX which is at CMOS 1.8V as shown below:
On the devkit, this signal is connected to M.2 E connector which is used for WiFi/BT modules, as shown below
Apart from the Level Shifting, this signal goes to M.2 E SUSCLK signal.
I was wondering why aren’t they using this signal for M.2 NVMe connector. What’s the differences that they are expecting between the SUSCLK signal for NVMe and WiFi connector? Is it necessary to replicate devkit setup with NVMe? What happens if we use CLK_OUT_32 with the NVMe SUSCLK?
This is related to the question - M.2 NVMe not detected on custom Xavier NX hardware (pcie link is down) - Jetson & Embedded Systems / Jetson Xavier NX - NVIDIA Developer Forums
That’s to ensure the clock meet the request of device. The 32khz clock is from PMIC in module and its characteristics are 20ppm, 12.5Pf loading and 1000ms startup time.
Thank you for your response. Details about the CLK_OUT_32 oscillator are welcome. However, I’m still confused about the “That’s to ensure the clock meet the request of the device” part.
Can we use that clock for M.2 NVMe? Do these characteristics not meet M.2 NVMe clock requirements?
This will help me in selecting a clock chip for our design.
That should be OK in theory, but you should check the datasheet of device to make sure about that, and better to keep a crystal as backup in your first build as it is different to devkit and not validated on devkit.
That makes sense to me! Thanks for the quick response.