I have two question for the control signal of CSI camera.
There are two camera master clock, CAM0_MCLK and CAM1_MCLK, in “Jetson TX1 Product OEM Design Guide” page45, section 8.0 fig21.
But, in “Jetson TX1 Developer Kit Carrier Board Schematics”, there are CAM2_MCLK, page5, J13A.E7.
Can use this signal, CAM2_MCLK? Is there a register for setting the CAM2_MCLK?
I want to synchronize the three cameras.
Three of the master clock “CAM0_MCLK, CAM1_MCLK, CAM2_MCLK” is can use the same signal clock source?
I’m also trying to get CAM2_MCLK to work; I’m able to set the rate, and disable/enable CAM1_MCLK using the entry at /sys/kernel/debug/clock/mclk3 but had no luck so far for CAM2_MCLK (I tried enabling it /sys/kernel/debug/clock/mclk and /sys/kernel/debug/clock/mclk2). Any suggestions?
Hi Trumany,
Thanks for your response, from the “Jetson_TX1_Developer_Kit_Carrier_Board_Design_Files_B02” I checked the squematics from the Camera Expansion and both the CAM2_MCLK and CAM1_MCLK seemed to go to 0ohm resistors, when I measure the signals from those resistors (that I was able to locate using the PCB information) I am able to check when I enable the CAM1_MCLK but doesn’t seem to work for the CAM2_MCLK. I wonder if I have the wrong squematics; this is the checksum of the file that I got
Does this mean that in the main module (the one with the SoC - not the carrier board) the CAM2_MCLK is not connected from the SoC to the extension port? We also have a custom carrier board where we are seeing the same problem, could you verify this?
There are 3 MCLK on CVM board to board connector, CAM0_MCLK, CAM1_MCLK, CAM2_MCLK
CAM2_MCLK/Pin E7 is not connected on CVM module board, The signal net have a prefix SNN_* that means not connected (Single Node Nets)
see attached schematic captured from P2180 schematic.
