Master clock question on CSI interface

Hi,

I am designing my own carrier. I want to support two CSI cameras. I have question on master clocks on CSI interface - MCLK02, MCLK03, MCLK04, MCLK05.

  1. Can I use MCLK02 and MCLK03? Basically can I use MCLK02 for camera#1, and MCLK03 for camera#2?
  2. Are MCLK02 - MCLK05 in the same phase? (I think MCLK05 is configured in GPIO mode, so it cannot be used as master clock. But I don’t need MCLK05 anyway.)
  3. What is the frequency of MCLK02 - MCLK05? Are they all 25 MHz? And is the frequency configurable using device-tree? If so, can you show me an example?
  4. I saw in “Jetson_AGX_Xavier_Series_Camera_Module_Hardware_Design_Guide_DG-09364-001_v1.2” section “2.2.2 Multiple Camera Case”, it shows an example of doing 6 cameras. It is only using one master clock MCLK02, then use a clock buffer to have a fan-out of 6. Do I need to do the same way as this example? Since I only need to support two cameras, does it mean that I can use the existing master clocks (MCLK02 and MCLK03) WITHOUT the need of clock buffer.
  5. What if I want to support frame-sync on two camera, do I need to make sure the two master clocks route to two cameras are in the same phase?

Thanks.

Hi, for camera design, please refer to the product design guide and camera module design guide in DLC. We don’t support other design than those in the guide.

Hi @Trumany

I want to know are both MCLK02 and MCLK03 25 MHz? (I cannot find this info in any document).
Also, can I use both MCLK02 and MCLK03?

Thank.

Have you checked the design guide in DLC? MCLK2/3/4/5 are available and support 25MHz.

Hi @Trumany

Thanks for your reply. Yes, I did check. I saw MCLK2-5 are available, but it doesn’t mention about clock frequency. It doesn’t mention whether they are in phase.

However, I found on l4t developer guide.
https://docs.nvidia.com/jetson/archives/l4t-archived/l4t-3243/index.html#page/Tegra%20Linux%20Driver%20Package%20Development%20Guide%2Fcamera_sensor_prog.html%23wwpID0E0Q50HA

It says:
"
Name of the input clock for the device. The default value is extperiph1.
The maximum frequency for extperiph1 is 24 MHz. If a frequency greater than 24 MHz is required, use an external clock source.
"

I also checked max freq reported by bpmp linux debugfs:

cd /sys/kernel/debug/bpmp/debug/clk
cat extperiph1/max_rate 
37090909
cat extperiph2/max_rate 
24000000
cat extperiph3/max_rate 
24000000
cat extperiph4/max_rate 
24000000

I am pretty sure that extperiph1 maps to MCLK2, and extperiph2 maps to MCLK3.
Does it mean that MCLK2 can go up to 37 MHz, but the rest of MCLK3-5 can only go up to 24MHz?
However, this is conflict with what LT4 developer guide saying, which says “maximum frequency for extperiph1 is 24 MHz”.

Which one is correct?

I want reference clock in 25 MHz. Shall I stay with MCLK2, or use an external clock generator?
Can you please give some guide?

Regards.

Hi NVIDIA,

Any update on this question.

Thanks.

hello lunarking1028,

the max frequency is set to 24MHz as our document mentioned.

however,
the MCLKs (i.e. extperiph1, extperiph2, extperiph3) were clock sourced from PLLP-OUT0, which is 408MHz, but we don’t recommend to set the divider to change the frequency.
so,
you may use the configuration and you should also confirm on the scope to check frequency.
if the clock is indeed 25Mhz, then it should be ok, thanks

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Hi @JerryChang

Thank you so much for your reply. It is very helpful.

Regards.