Dear experts,
Currently, I am using a Versaclock5 clock generator in order to provide clock sources to multiple camera sensors with different frequencies (and higher than the default frequency provided by the default MCLK pins of the MIPI-CSI2 camera interfaces).
The clock generator node is as below :
i2c@c240000 {
vc5: clock-generator@6a {
compatible = "idt,5p49v5925";
reg = <0x6a>;
#clock-cells = <1>;
clocks = <&ref25>;
clock-names = "xin";
/*
* ASSIGNED CLOCKS CONFIGURATION
* Here we select OUT1 (index 1) and OUT2 (index 2) to be configured at boot
*/
assigned-clocks = <&vc5 1>, <&vc5 2>;
assigned-clock-rates = <37125000>, <74250000>; /* OUT1 = 37.125 MHz, OUT2 = 74.25 MHz */
/* Electrical characteristics for individual outputs */
OUT1 {
idt,mode = <VC5_CMOS>;
idt,voltage-microvolt = <1800000>;
idt,slew-percent = <85>;
};
OUT2 {
idt,mode = <VC5_CMOS>;
idt,voltage-microvolt = <1800000>;
idt,slew-percent = <85>;
};
};
};
How should I replace the default clock-names, mclk properties of the camera node(s) (which is/are the clock consumer(s)) in this case, please ?
imx296_a@1a {
status = "okay";
# clocks = <&bpmp_clks TEGRA234_CLK_EXTPERIPH1>, <&bpmp_clks TEGRA234_CLK_EXTPERIPH1>;
# clock-names = "extperiph1", "pllp_grtba";
# mclk = "extperiph1";
# clock-frequency = <27000000>; // Max. freq supported by the Jetson, ignored if an on-module oscillator is used.
clocks = <&vc5 1>;
clock-names = "mclk"; // or "inck" depending on camera driver
clock-frequency = <37125000>;
reset-gpios = <&tegra_main_gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
};
Knowing that I set the the clock-names as above (and omitting the mclk property as I haven’t known what to put), I got below error :
[ 12.562879] imx296 9-001a: unable to get clock mclk
[ 12.562882] imx296 9-001a: unable to power get
[ 12.562884] imx296 9-001a: tegra camera driver registration failed
Thanks in advance and best regards,
Khang
Khang