I am busy designing my own Jetson Nano carrier to support NVMe SSD storage. My design was mostly copied from the Jetson Xavier design but I have questions related to the following as highlighted in the attached schematic:
Blue and Green boxes: The Xavier design implements a dedicated SUSCLK_32KHZ as shown in the blue box. If I read the Nano documentation correctly, then I do not need the blue box and I will be able to get the SUSCLK_32KHZ directly from the Jetson Nano as shown in the green box. Is this correct?
Pink box: Why does Xavier implement I2C and ALERT? According to the PCIe specification for Key-M implementation there is no mention of I2C and ALERT signals. Have I missed something here?
General comments on the schematic are welcome.
M.2 Key M Schematic.pdf (198 KB)