NVMe design for Jetson Nano

Robotics & Edge Computing Jetson & Embedded Systems Jetson Nano
1

Hi,

I am busy designing my own Jetson Nano carrier to support NVMe SSD storage. My design was mostly copied from the Jetson Xavier design but I have questions related to the following as highlighted in the attached schematic:

  1. Blue and Green boxes: The Xavier design implements a dedicated SUSCLK_32KHZ as shown in the blue box. If I read the Nano documentation correctly, then I do not need the blue box and I will be able to get the SUSCLK_32KHZ directly from the Jetson Nano as shown in the green box. Is this correct?

  2. Pink box: Why does Xavier implement I2C and ALERT? According to the PCIe specification for Key-M implementation there is no mention of I2C and ALERT signals. Have I missed something here?

General comments on the schematic are welcome.

Thanks,

Willie

M.2 Key M Schematic.pdf (198 KB)

2

M.2 slots have particular “keys”, and certain parts are in common with all keys (for example, even if two cards of the wrong key are somehow inserted wrong, despite not functioning, there probably won’t be any permanent damage). Go here to Wikipedia as a reference:

https://en.wikipedia.org/wiki/M.2

Then search for “M.2 module keying and provided interfaces”. The table there will show that a key M contains more than PCIe. There is also SATA and SMBus. Note that not all interfaces are necessarily implemented on all key M slots on all hardware in the world, but SMBus uses i2c.

3

Thanks linuxdev - I understand the different keys, however:

I am still unsure why you need the SMBus (I2C) and ALERT interface signals? This seems like an old interface being implemented for NVMe devices that uses SMBUS to communicate information to the system. Are these signals (SMBus and ALERT) really needed?

To my questions in the original post - anyone from Nvidia that can respond?

Thanks

4

@Nvidia

  1. Blue and Green boxes: The Xavier design implements a dedicated SUSCLK_32KHZ as shown in the blue box. If I read the Nano documentation correctly, then I do not need the blue box and I will be able to get the SUSCLK_32KHZ directly from the Jetson Nano as shown in the green box. Is this correct?
5

@Nvidia ?

6

Hi, 32khz clock is provided by module on nano, and I2C is NOT MUST, in fact it is unconnected on dev kit. You can refer to the reference schematic of nano carrier board in DLC for more info of this.

7

Hi @willie.erasmus, @linuxdev,

considering your schematic, were you able to build one on the Jetson nano from Xavier schematics. how did it do? what should I look out for when designing mine? I will appreciate any help you can proffer to me.

Please know I’m redesigning the carrier board for my case needs only. Thanks

8

Hi @bvgohmslf,

Sorry for the delayed response. I’ve just finished the schematic for the PCIe-to-NVMe interface for the Nano. I have some questions that I need to clarify. Have you finished your design? Maybe we can exchange notes?

1 Like
9

Hi @willie.erasmus,

I haven’t finished the design yet and will be open to exchange notes. When do we start?

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Hi@ willie.erasmus,i have finished NVMe on both NX and Nano.