Is the swapping of polarity for a single TX or RX differentially pair handled automatically by the USB3 and PCIE interfaces?
The specification lists that it is possible but it’s not clear what the implementation is. In contrast, CSIO pins have a lane polarity parameter in the device tree, but I haven’t seen similar solutions for USB3 or PCIE. This feels like a stupid question, but I don’t want to chance an entire design on how I think lane polarity works.