适配T5000的自研载板，需要新增两个PWM风扇。对应的TACH信号有什么限制？是否可以用的T5000模块的K49 H51 H52 F56 pin，GPIO 25 26 27 36？如图
Hi hyla_huang1,
What’s the Jetpack version in use?
You can refer to https://elinux.org/Jetson/L4T/peripheral/#Mapping_5 for the PWM mapping.
Please also refer to Support for Independent Dual-Fan PWM/Tachometer Configuration - #4 by WayneWWW for the dual-fan on Thor.
Jetpack 7.2
Okay, please enable tachometer@810c5d0000 in device tree.
请问，PWM2和PWM3默认对应的TACH信号分别是哪个引脚？谢谢！
Hi @hyla_huang1 & @KevinFFF ,
I noticed that in the Thor-Soc-TRM_DP-11881-002_v1.2p.pdf document available from theNvidia jetson download center Section 7.9, Pulse Width Modulator (PWM) mentions that, in addition to the default PWM4 used for fan control, a second fan can be controlled using PWM5, which is labeled as “2nd Fan control or spare,” as shown in the figure below.
In the Pinmux configuration, it appears as follows:
PWM5:
FAN_TACH1:
So I’m not sure whether configuring PWM2 and PWM3 for fan control would cause any issues, given that the TRM specifically references PWM4 and PWM5 for fan control. Could you clarify whether using PWM2 and PWM3 for fan control is supported or if there are any potential limitations or side effects?
Thanks!!
Based on the current TRM and pinmux information, PWM4 is the default fan control and PWM5/FAN_TACH1 is the documented path for a second fan.
We do not currently have official confirmation that PWM2/PWM3 are supported for fan control on T5000, so I would not recommend them as the default solution.
我看到 source/hardware/nvidia/t264/nv-public/tegra264.dtsi 中除了你提到的 tachometer@810c5d0000 ，还有一个 tachometer@810c5c0000
1.对应关系是不是 PWM4对应tachometer@810c5c0000，PWM5对应tachometer@810c5d0000 ？
2.如果需要再增加一路PWM，应该如何修改？有没有资料可以参考？
sudo dtc -I fs -O dts -o ~/live.dts /proc/device-tree
grep pwm live.dts -A5
pwm@810c610000 {
clock-names = "pwm";
resets = <0x02 0x1c>;
clocks = <0x02 0x1e>;
nvidia,hw-instance-id = <0x09>;
#pwm-cells = <0x02>;
compatible = "nvidia,tegra264-pwm";
status = "disabled";
reg = <0x81 0xc610000 0x00 0x10000>;
phandle = <0x2ac>;
reset-names = "pwm";
};
iommu@8806000000 {
nvidia,tegra264-tlbi-race-fix;
interrupts = <0x00 0xe1 0x01 0x00 0xe2 0x01>;
--
pwm@810c620000 {
clock-names = "pwm\0parent";
resets = <0x02 0x17>;
clocks = <0x02 0x19 0x02 0x16>;
nvidia,hw-instance-id = <0x0a>;
#pwm-cells = <0x02>;
compatible = "nvidia,tegra264-pwm";
status = "okay";
reg = <0x81 0xc620000 0x00 0x10000>;
phandle = <0x2ad>;
reset-names = "pwm";
};
i2c@810c670000 {
#address-cells = <0x01>;
clock-names = "div-clk\0parent";
--
#pwm-cells = <0x02>;
compatible = "nvidia,pwm-tegra264-tachometer";
status = "okay";
reg = <0x81 0xc5c0000 0x00 0x10>;
reset-names = "tach";
};
--
pwm@c6a0000 {
resets = <0x02 0x1a>;
clocks = <0x02 0x1c>;
nvidia,hw-instance-id = <0x04>;
#pwm-cells = <0x02>;
compatible = "nvidia,tegra264-pwm";
status = "okay";
reg = <0x00 0xc6a0000 0x00 0x10000>;
phandle = <0x240>;
reset-names = "pwm";
};
psc@e0e0000 {
iommus = <0x50 0x2300>;
nvidia,sidconfig = <0x00>;
--
#pwm-cells = <0x02>;
compatible = "nvidia,pwm-tegra264-tachometer";
status = "disabled";
reg = <0x81 0xc5d0000 0x00 0x10>;
reset-names = "tach";
};
--
pwm@810c5e0000 {
clock-names = "pwm";
resets = <0x02 0x18>;
clocks = <0x02 0x1a>;
nvidia,hw-instance-id = <0x02>;
#pwm-cells = <0x02>;
compatible = "nvidia,tegra264-pwm";
status = "disabled";
reg = <0x81 0xc5e0000 0x00 0x10000>;
phandle = <0x2a9>;
reset-names = "pwm";
};
pcie@a808420000 {
#address-cells = <0x03>;
dma-coherent;
--
pwm@810c600000 {
clock-names = "pwm";
resets = <0x02 0x1b>;
clocks = <0x02 0x1d>;
nvidia,hw-instance-id = <0x05>;
#pwm-cells = <0x02>;
compatible = "nvidia,tegra264-pwm";
status = "disabled";
reg = <0x81 0xc600000 0x00 0x10000>;
phandle = <0x2ab>;
reset-names = "pwm";
};
--
pwm@810c5f0000 {
clock-names = "pwm\0pll_aon";
resets = <0x02 0x19>;
clocks = <0x02 0x1b 0x02 0xa0>;
nvidia,hw-instance-id = <0x03>;
#pwm-cells = <0x02>;
compatible = "nvidia,tegra264-pwm";
status = "okay";
reg = <0x81 0xc5f0000 0x00 0x10000>;
phandle = <0x2aa>;
reset-names = "pwm";
};
--
nvidia,max-pwm-gear = <0x00>;
--
pwm-fan {
cooling-levels = <0x4d 0x66 0x8c 0xc0 0xff>;
compatible = "pwm-fan";
phandle = <0x226>;
pwms = <0x240 0x00 0x9c40>;
#cooling-cells = <0x02>;
};
--
pwm9 = "/bus@0/pwm@810c610000";
i2s7_port = "/bus@0/aconnect@9000000/ahub@9630000/i2s@92e0000/ports/port@1";
xbar_amx4_in2 = "/bus@0/aconnect@9000000/ahub@9630000/ports/port@47/endpoint";
admaif19_port = "/bus@0/aconnect@9000000/ahub@9630000/admaif@9610000/ports/port@13";
sfc2_cif_out = "/bus@0/aconnect@9000000/ahub@9630000/sfc@9710000/ports/port@1/endpoint";
xbar_amx2_in1_port = "/bus@0/aconnect@9000000/ahub@9630000/ports/port@3c";
--
soc_fan = "/pwm-fan";
dmic2_port = "/bus@0/aconnect@9000000/ahub@9630000/dmic@9310000/ports/port@1";
xbar_dmic2 = "/bus@0/aconnect@9000000/ahub@9630000/ports/port@29/endpoint";
xbar_mix_in3_port = "/bus@0/aconnect@9000000/ahub@9630000/ports/port@75";
xbar_asrc_in6_port = "/bus@0/aconnect@9000000/ahub@9630000/ports/port@8c";
smmu3_hwpm = "/bus@0/smmu-hwpm@8806a30000";
--
pwm5 = "/bus@0/pwm@810c600000";
top_hsp3 = "/bus@0/tegra-hsp@8d00000";
xbar_amx5_in4_port = "/bus@0/aconnect@9000000/ahub@9630000/ports/port@4e";
xbar_i2s5 = "/bus@0/aconnect@9000000/ahub@9630000/ports/port@24/endpoint";
isp = "/bus@0/host1x@8181200000/isp@8188800000";
sdmmc1_3v3 = "/bus@0/pmc@c800000/sdmmc1-3v3";
--
pwm10 = "/bus@0/pwm@810c620000";
adx3_out2_port = "/bus@0/aconnect@9000000/ahub@9630000/adx@95b0000/ports/port@2";
xbar_mix_in9_port = "/bus@0/aconnect@9000000/ahub@9630000/ports/port@7b";
agic_page0 = "/bus@0/aconnect@9000000/interrupt-controller@9960000";
gpu_sw_shutdown = "/thermal-zones/gpu-thermal/trips/gpu-sw-shutdown";
pmu_tbu10_smmu3 = "/pmu_tbu10_smmu3@8806000000";
--
pwm3 = "/bus@0/pwm@810c5f0000";
xbar_amx4_in2_port = "/bus@0/aconnect@9000000/ahub@9630000/ports/port@47";
xbar_i2s3 = "/bus@0/aconnect@9000000/ahub@9630000/ports/port@22/endpoint";
asrc_out4_ep = "/bus@0/aconnect@9000000/ahub@9630000/asrc@9850000/ports/port@a/endpoint";
tegra_adx2 = "/bus@0/aconnect@9000000/ahub@9630000/adx@95a0000";
xbar_amx3_in1 = "/bus@0/aconnect@9000000/ahub@9630000/ports/port@41/endpoint";
--
pwm4 = "/bus@0/pwm@c6a0000";
top_hsp2 = "/bus@0/tegra-hsp@8c00000";
xbar_i2s4 = "/bus@0/aconnect@9000000/ahub@9630000/ports/port@23/endpoint";
tegra_adx3 = "/bus@0/aconnect@9000000/ahub@9630000/adx@95b0000";
xbar_adx3_out1 = "/bus@0/aconnect@9000000/ahub@9630000/ports/port@60/endpoint";
xbar_amx3_in2 = "/bus@0/aconnect@9000000/ahub@9630000/ports/port@42/endpoint";
--
pwm2 = "/bus@0/pwm@810c5e0000";
top_hsp0 = "/bus@0/tegra-hsp@8800000";
xbar_mix_in5_port = "/bus@0/aconnect@9000000/ahub@9630000/ports/port@77";
xbar_i2s2 = "/bus@0/aconnect@9000000/ahub@9630000/ports/port@21/endpoint";
replicator_in_port0 = "/replicator_soc@10060000/in-ports/port/endpoint";
xbar_ope1_in_ep = "/bus@0/aconnect@9000000/ahub@9630000/ports/port@8f/endpoint";
--
clock-names = "osc\0clk_s\0jtag_reg\...\0pwm10\0pwm2\0pwm3\0pwm4\0pwm5\0pwm9\0qspi0\0qspi0_2x_pm\...\
810c5c0000 is TACH0 and 810c5d0000 is TACH1, so it is reasonable to read the current design as PWM4 + TACH0 and PWM5 + TACH1.
For the three PWM nodes, c6a0000 = PWM4, 810c5f0000 = PWM3, and 810c620000 = PWM10.
You can also refer to https://elinux.org/Jetson/L4T/peripheral/#Mapping_5 for detailed mapping.
If you want to add one more PWM, please enable another available PWM node in DT and update the pinmux accordingly
感谢你的耐心解释！
我在 source/hardware/nvidia/t264/nv-public/include/kernel-t264/dt-bindings/reset/tegra264-rst.h 中找到两个TACH相关的定义：TEGRA264_RESET_TACH1 和 TEGRA264_RESET_TACH0，但是也仅仅找到这两个。
我想了解的问题是，如果再增加第三个pwm风扇，是否无法使用新的 TACH 了？自己定义一个类似 TEGRA264_RESET_TACH2 这样的定义，无法得到系统的支持吧？
Hi, based on the current T264 BSP/driver exposure, we only see support for TACH0 and TACH1, and there is no official TACH2 definition or driver path at this time.
So adding a custom TEGRA264_RESET_TACH2 definition alone would not be sufficient to get system support, because this also depends on BPMP ABI, driver support, and actual HW resource exposure.
A third PWM output may still be possible, but a third tach input is not something we can recommend based on the current official software support.