tegra uart - THRE reset

I have done some work to get the Tegra UART working with Xen’s 16550 driver. In this process I came across an inconsistency between the behavior I am seeing on x86 PC vs Tegra UARTs. The UART is configured for FIFO / PIO / Interrupt driven.

On the x86 PC’s UART, once the interrupt is asserted for THRE, an IIR read will reset (or mask) this interrupt until re-triggered by flipping the IER (or after transmitting some data).

On the Tegra’s UART, once the interrupt is asserted for THRE, an IIR read appears to have no effect. It either fails to de-assert, or immediately re-asserts, causing the interrupt handler to spin.

Looking at the Linux kernel (serial-tegra) driver, perhaps this behavior is expected? It appears that it masks off THRE interrupts in the IER, until start_tx re-enables it?
http://lxr.free-electrons.com/source/drivers/tty/serial/serial-tegra.c#L718

I took the same approach with the Xen driver to get it working, but I was curious if anyone had an explanation for the behavior I’m seeing? :) Thanks!

I don’t know if this is related or not, but the UARTs in the SoC have the capability of being in 16450 mode or 16550 mode. I think 16450 is default. Hardly anyone would use a 16450 anymore, but unless someone set up the UART for 16550 mode (and I do not know which mode current software sets up), the UART will behave slightly different from the desktop UART (which would be 16550/16550A). Mode setting is described in the Tegra K1 TRM. See:
https://developer.nvidia.com/tegra-k1-technical-reference-manual