The PCIE C3 controller is unable to recognize the device

我们得PCIe C3接口接了一个2lane的ASM1806的switch芯片,但是在系统中lspci无法发现设备,下列是相关的日志信息,
同时,我们还有另外一块适配AGX ORIN的载板,也已经适配了Thor模组,Thor 的PCIe C3对应的信号引到了M.2 Key M上, 也识别不到PCIe设备,这个载板使用AGX ORIN的时候,对应的PCIe功能是正常的。所以硬件电路是没有问题的。

[    7.428573] tegra264-pcie a808440000.pcie: host bridge /bus@0/pcie@a808440000 ranges:
[    7.436242] tegra264-pcie a808440000.pcie:      MEM 0x0038000000..0x003fffffff -> 0x0038000000
[    7.444971] tegra264-pcie a808440000.pcie:      MEM 0xb8c0000000..0xc07fffffff -> 0xb8c0000000
[    7.462097] tegra264-pcie a808440000.pcie: ECAM at [mem 0xb8b0000000-0xb8bfffffff] for [bus 00-ff]
[    8.471640] tegra264-pcie a808440000.pcie: PCIe Controller-3 Link is DOWN
[    8.471716] tegra264-pcie a808440000.pcie: PCI host bridge to bus 0003:00
[    8.476635] pci_bus 0003:00: root bus resource [mem 0x38000000-0x3fffffff]
[    8.483615] pci_bus 0003:00: root bus resource [mem 0xb8c0000000-0xc07fffffff pref]
[    8.491298] pci_bus 0003:00: root bus resource [io  0x600000-0x7fffff] (bus address [0x84000000-0x841fffff])
[    8.501107] pci 0003:00:00.0: [10de:22da] type 01 class 0x060400 PCIe Root Port
[    8.508450] pci 0003:00:00.0: PCI bridge to [bus 01-ff]
[    8.513880] pci 0003:00:00.0: PME# supported from D0 D3hot
[    8.520659] pci 0003:00:00.0: bridge window [io  0x1000-0x0fff] to [bus 01-ff] add_size 1000
[    8.527622] pci 0003:00:00.0: bridge window [mem 0x00100000-0x000fffff 64bit pref] to [bus 01-ff] add_size 200000 add_align 100000
[    8.539491] pci 0003:00:00.0: bridge window [mem 0x00100000-0x000fffff] to [bus 01-ff] add_size 200000 add_align 100000
[    8.566382] pci 0003:00:00.0: bridge window [io  0x600000-0x600fff]: assignedbit pref]: assigned
[    8.573718] pci 0003:00:00.0: PCI bridge to [bus 01-ff]
[    8.578957] pci 0003:00:00.0:   bridge window [io  0x600000-0x600fff]
[    8.585244] pci 0003:00:00.0:   bridge window [mem 0x38000000-0x381fffff]
[    8.592226] pci 0003:00:00.0:   bridge window [mem 0xb8c0000000-0xb8c01fffff 64bit pref]
[    8.600262] pci_bus 0003:00: resource 4 [mem 0x38000000-0x3fffffff]
[    8.606543] pci_bus 0003:00: resource 5 [mem 0xb8c0000000-0xc07fffffff pref]
[    8.613528] pci_bus 0003:00: resource 6 [io  0x600000-0x7fffff]
[    8.619466] pci_bus 0003:01: resource 0 [io  0x600000-0x600fff]
[    8.625402] pci_bus 0003:01: resource 1 [mem 0x38000000-0x381fffff]
[    8.631688] pci_bus 0003:01: resource 2 [mem 0xb8c0000000-0xb8c01fffff 64bit pref]
[    8.641612] pcieport 0003:00:00.0: Adding to iommu group 10
[    8.645547] pcieport 0003:00:00.0: PME: Signaling with IRQ 195
[    8.651744] pcieport 0003:00:00.0: AER: enabled with IRQ 182
[    8.656514] pcieport 0003:00:00.0: pciehp: Slot #0 AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ Interlock- NoCompl+ IbPresDis- LLActRep+
[    8.671043] pcieport 0003:00:00.0: pciehp: Slot(0): Card present
[    8.671433] pcieport 0003:00:00.0: DPC: enabled with IRQ 181
[    8.681642] pcieport 0003:00:00.0: DPC: error containment capabilities: Int Msg #1, RPExt+ PoisonedTLP+ SwTrigger+ RP PIO Log 4, DL_ActiveErr+

跟PCIE C3控制器相关的内容修改如下:

#y-c28-agx-thor-382.conf文件
#UPHY_CONFIG="tegra264-mb1-bct-uphy-lanes-p4071-0000.dts";
UPHY_CONFIG="";
#BPFDTB_FILE="tegra264-bpmp-3834-0008-4071-xxxx.dtb";
BPFDTB_FILE="tegra264-bpmp-3834-0008-4071-xxxx-c28.dtb";
#PINMUX_CONFIG="tegra264-mb1-bct-pinmux-p3834-xxxx-p4071-0000.dts";
PINMUX_CONFIG="tegra264-mb1-bct-pinmux-p3834-xxxx-p4071-0000-c28.dts";
#DTB_FILE="tegra264-p4071-0000+p3834-0008-nv.dtb";
DTB_FILE="y-c28-agx-thor-382.dtb";


#tegra264-bpmp-3834-0008-4071-xxxx-c28.dts文件
		pcie@3 {
			//status = "disabled";	/* Modify by chenxi to support y-c28's PCIE */
			status = "okay";
			pcie-id = <0x03>;
			pcie-mode = <0x01>;
			max-link-speed = <0x05>;
			hot-plug-capable = <1>;	/* Add by chenxi */
		};

	uphy {
		status = "okay";
		//uphy0-config = <0x07>;
		uphy0-config = <0x06>;	/* Modify by chenxi to support y-c28 pcie C3 */


#tegra264-mb1-bct-pinmux-p3834-xxxx-p4071-0000-c28.dts文件
pex_l3_clkreq_n_pb4 {
				nvidia,pins = "pex_l3_clkreq_n_pb4";
				nvidia,function = "pe3_clkreq_l";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,drv-type = <TEGRA_PIN_1X_DRIVER>;
				nvidia,e-io-od = <TEGRA_PIN_ENABLE>;
				nvidia,e-lpbk = <TEGRA_PIN_DISABLE>;
			};

			pex_l3_rst_n_pb5 {
				nvidia,pins = "pex_l3_rst_n_pb5";
				nvidia,function = "pe3_rst_l";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,drv-type = <TEGRA_PIN_1X_DRIVER>;
				nvidia,e-io-od = <TEGRA_PIN_ENABLE>;
				nvidia,e-lpbk = <TEGRA_PIN_DISABLE>;
			};

# dtb文件
/* PCIe C3 */
        pcie@a808440000 {
            status = "okay";
        };
1 Like



通过查看pinmux表发现,PCIe控制器3的始终是未使用的状态,我修改为使用状态过后,发现pinmux对应的dts没有任何的变化。
请问我应该如何修改?

我们将尝试将UPHY_RX/TX6和UPHY_RX/TX7进行交换,
参照P3971的原理图,这两个lane的顺序不太一样,还请帮忙确定一下,除了交换顺序之外,极性是否需要翻转

我们通过飞线的方式,交换了UPHY6和UPHY7的通道位置,是可以正常工作了。这个问题,是否可以通过修改软件的方式,来交换UPHY6和UPHY7的位置?

No, it is not possible.

问题已经解决了,使我们硬件设计的问题。

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