TX2 + Auvidea J100 power sequences

Hi,

I would like to use TX2 with a J100 carrier board.

I can see in the documentation “NVIDIA Jetson TX2/TX2i OEM Product Design Guide” that there are few recommandation to manage “uncontrolled power removal” but I wanted to be sure that those recommandations are integrated in the Auvidea carrier board.
I’m trying to understand if we can hot-plug the power supply with TX2 mounted on the J100 carrier board or if we have to add specific components between the power supply and the carrier board to manage power-up and power-down sequences?

Unfortunately, the documentation from Auvidea is really light and I’m still waiting feedback from them since few weeks.

Thank you for your help

Hi Julien,

the J100 features a MCU (micro controller) which watches the power connection to the J100 and the TX2. If power is removed briefly or if the power input voltage drops below a certain point, it will power cycle the CPU and monitor that the TX2 reboots. This ensures that the TX2 system is always on.

Furthermore we have developed a supercap add-on module (38300), which gives the TX2 some extra time (30 seconds to 10 minutes) in a power down case, to gracefully power down and inform a cloud or server via a communications link that power is lost. It integrates 4 or 8 supercaps with 25 or 70 Farad each. Same size as TX2 and J100. May be mounted underneath. This module will be announced shortly.

Please let me know, if you have further questions.

Hi,

Thank you for your reply.

I understand that the MCU watches the voltage and power cycle if needed. Is the MCU watches for a low voltage level to trigger quick power-down sequence ?
Typically, that’s happening when battery is empty (low voltage protection of the battery cut-off).

We are not looking for doing complex tasks like sending a message to inform cloud server. We just want a clean power-down as described page 12 of the “TX2 OEM product design guide” and below :

“t1 VDD_IN Removed in uncontrolled manner
t2 VIN_PWR_BAD detection “sees” drop in VDD_IN & is
asserted to start uncontrolled power-down sequence.
RESET_OUT# & CARRIER_PWR_ON are driven low via
PMIC sequence soon after. Carrier board power &
Jetson TX2 power begin to ramp down.
Carrier board power (mainly 1.8V rail
associated with interface pins connected to
Jetson TX2) should ramp down faster so it is
off before the Jetson TX2 main 1.8V rail is
off.”

It seems that it takes 20ms to do that. Is the carrier board (with MCU) manage this power-down sequence (and have enough energy stored in internal capacitor to do this) ?

The external supercap add-on seems way overrated as we only need 20ms for a clean power down sequence.

Thank you in advance