My company is testing a new revision of a carrier board we designed for the Jetson SODIMM style modules, we’re currently having issues with the power up of the TX2 NX module, the carrier board works ok with the Nano though.
For the TX2 NX, we found that some power supplies work, while others do not, even though they can all provide over 5A continuous. In particular, we found that the ones that do not work either seem to have a brief brownout on the Jetson supply rail on power up (when viewed on an oscilloscope, the PWR_EN also goes low briefly during those brownouts), or, they only have the PWR_EN signal come up very briefly.
We thought we could resolve the issue by adding buffer capacitance (roughly 990 uF in addition to the the 200 uF we had previously) at the module supply pins, but all that did was induce the second failure case even on the supply that previously worked, which is confusing to us. We’re not sure yet as we haven’t checked it with the oscilloscope, but is it possible that the TX2 NX module is holding the SHUTDOWN_REQ signal low? Our power sequencer setup has that as an input, and sets PWR_EN low if SHUTDOWN_REQ is low. Could it be something like the module PMIC latching the signal low due to some early power low failure condition? In particular, could it stay latched on if the module itself still had power applied to its supply pins, even though the PWR_EN signal is low?
Thanks for your guys’ help in advance!
did you refer to Jetson TX2 NX Product Design Guide to have product development?
please review [5.1 Power Supply and Sequencing] for the detail of the power supply and sequencing for the Jetson TX2 NX module.
Yes we did, unfortunately I was confused and our level shifter supplies that should be enabled by SYS_RESET are instead independently enabled, so the level shifters are coming up before the TX2 NX. What we did though was that we disabled those I/O level shifter supplies, so for these tests there is no I/O interfering with boot up (though on our board did boot up initially even with independently enabled shifters when using certain power supplies). Is there a min/max time window between VDD_IN and SHUTDOWN_REQ going high and PWR_EN going high that must be met?
In addition we also figured out that the earlier issue after adding the extra buffer capacitance was with our sequencer itself, now that we’ve corrected that, we meet the diagram I pasted above, though the SYS_RESET line still does not come up. Currently our delay between VDD_IN/SHUTDOWN_REQ coming up and PWR_EN going high is about 2 sec.
Thanks for taking a look!
Can you take and share a photo of the power on sequence waveform on oscilloscope with your board? Basically it is a simple logic/timing as listed in the figure of power up sequence in design guide. And what is the difference between your design and reference, like P3509 board?
So sorry, took a bit to take oscilloscope shots as we tried a few different things, here it is now. traces are as such: trace1 = board 5V, trace2 = PWR_EN to TX2 NX, trace3 = SHUTDOWN_REQ from TX2; trace4 = 5V rail at TX2 NX (after e-fuse) :
As you can see, we have a fair amount of time between when the rails come up and when PWR_EN goes high, yet the module does not boot (SYS_RESET) stays low. We suspect it could be because of a very short power sag, is there a recommended minimum bulk capacitance for the TX2 NX module? The power section of the design guide does not go into that.
This is a zoom in of the suspected power sag area, this is before we added some external caps but they are a bit far away from the module, we can’t really get any bulk capacitance right at the pins (we are adding wire leads of ~1-2 inches from the pins to the capacitors). Picture above is after we added ~1000uF of capacitance. I don’t know whether that capacitance is actually effective though given the wire leads.
Hi, you can check your power design based on P3509 schematic in DLC. Also please note, for your description “so the level shifters are coming up before the TX2 NX”, all carrier supplies should be turn on after module so that the shared interface pins status won’t be affected during power on.
That is correct the level shifters come up before the TX2 NX, but in for this experiment instance we disabled the level shifters so that they stay high impedance, thus TX2 NX pins are not affected on power on
Have you compare your design to P3509/P3449 schematic? The power on sequence looks fine, not sure why it can’t boot. It might be some carrier parts issue which cause the interface/power part abnormal.
This topic was automatically closed 14 days after the last reply. New replies are no longer allowed.