I am designing a carrier board using Jetson Xavier NX. Could you please tell me about the SHUTDOWN_REQ* signal (pin 233)?
Question 1: In Table 5-1. on page 11 of the Design Guide, the Direction of the SHUTDOWN_REQ* signal is “Output” and the Pin Type is “Open Drain, 5.0V”. Is this signal used inside the JETSON module?
Question 2: In Figure 5-2. Power Up Sequence on page 14 of the Design Guide, it seems to say that “400ms min.” is required from the rising edge of the SHUTDOWN_REQ* signal to the rising edge of the POWER_EN signal.
Is this required? In our carrier board, we have ensured 400ms or more from the rising edge of VDD_IN to the rising edge of the POWER_EN signal, but the SHUTDOWN_REQ* signal and the POWER_EN signal rise at the same time. Is this a problem?
Question 3: On page 16 of the Design Guide, in Figure 5-6. Power Down, the falling edge of the SHUTDOWN_REQ* signal is earlier than the falling edge of the POWER_EN signal. Is it OK if the falling edges of the SHUTDOWN_REQ* and POWER_EN signals are almost simultaneous?
If the SHUTDOWN_REQ* signal needs to fall first, what is the minimum period required from the falling edge of the SHUTDOWN_REQ* signal to the falling edge of the POWER_EN signal?
I would appreciate your help with the above three points.
For custom design, SHUTDOWN_REQ_N is output only no matter whether it is used inside module.
400ms is necessary. SHUTDOWN_REQ_N should rise with VDD_IN together, why does it rise later on your board?
As said in Note: SHUTDOWN_REQ* must always be serviced by the carrier board to toggle POWER_EN from high to low, even in cases of sudden power loss. The timing is not strict. The 10ms is the key, your design should guarantee that.
I understand that the SHUTDOWN_REQ* signal is not used inside the JETSON module.
In our carrier board, we use a reset IC with an open-drain output (about 600mS delay) to ensure more than 400mS from the rising edge of VDD_IN to the rising edge of the POWER_EN signal. The POWER_EN signal is generated by connecting the reset IC output and the SHUTDOWN_REQ* signal. Therefore, the POWER_EN signal and the SHUTDOWN_REQ* signal appear to rise simultaneously on the carrier board.
About 600mS is ensured from the rising edge of VDD_IN to the rising edge of the POWER_EN signal.
In question 1, you said that the SHUTDOWN_REQ* signal is not used inside the JETSON, but please tell me why it must rise together with VDD_IN in the power-up sequence. If it is not used inside the JETSON module, I don’t think it will affect the operation of the JETSON module.
In our carrier board, we detect a power loss before the VDD_IN voltage drops below 4.2V and pull the POWER_EN signal to low. At the same time, the SHUTDOWN_REQ* signal is pulled to low from the carrier board. Is this not enough?
Your such design is not validated and we don’t suggest to do that even though it looks fine on your board. Generally you should use SHUTDOWN_REQ_N not VDD_IN to toggle POWER_EN.
I understand that you have not verified our design. However, what I would like to know is whether the SHUTDOWN_REQ* signal affects the JETSON module.
Our carrier board ensures that there is more than 10mS between the falling edge of the POWER_EN signal and the VDD_IN voltage dropping to 3.0V. Furthermore, the SHUTDOWN_REQ* signal is pulled low from the carrier board at the same time as the falling edge of the POWER_EN signal.
Also, there is about 600mS between the rising edge of the VDD_IN voltage and the rising edge of the POWER_EN signal.
I also understand that the SHUTDOWN_REQ* signal is an output signal of the JETSON module and is not used internally.
About question 2
I described that in our carrier board, the SHUTDOWN_REQ* signal and the reset IC output signal are connected to generate the POWER_EN signal. Because the open-drain outputs are ANDed with each other, it looks that the rising edge of the SHUTDOWN_REQ* signal is delayed by being pulled low by the reset IC output.
Can your such AND design fulfill the Figure 5-4. Power Down (Initiated by SHUTDOWN_REQ* Assertion)? SHUTDOWN_REQ_N could be triggered by sw, power bad or thermal.
