On our custom board we see the following behaviour of the #shutdown_req signal when turning off the power supply to simulate a sudden loss of power. First, we see VDD_IN dip quickly, which then leads to #shutdown_req oscillating for ~12ms. As we are following the requirements for power sequencing in case of sudden power loss as outlined in the design guide, I was hoping you could shed some light on what might be happening here. We are not driving the signal in any way, it is connected to the gate of a MOSFET with a 100k pull-down, nothing more.
As you can see in DG: SHUTDOWN_REQ* must always be serviced by the carrier board to toggle POWER_EN from high to low, even in cases of sudden power loss.
Which is what we are doing. Our circuitry simply looks like this:
We also confirmed that POWER_EN correctly mirrors #SHUTDOWN_REQ. So why would #SHUTDOWN_REQ (and by extension POWER_EN) oscillate wildly like we are seeing?
No clue on this. For custom board, you may need to compare to reference to find out root cause. In addition, there is a checklist sheet attached in the Design Guide which might be helpful.
The checklist (and the design guide) only define:
“If SHUTDOWN_REQ* goes low due to thermal shutdown, sudden power loss, etc., POWER_EN must be deactivated (low) as soon as possible.”
Which we are following. Comparing our design to the reference design is difficult, as we do not use the power-button micro-controller. From the definition in the design guide it is not clear what this MCU is actually doing in response to SHUTDOWN_REQ asserting. Maybe you could explain this more clearly?
Shutdown_req is to trigger POWER_EN through MCU as you can see in the Figure 6-6. Power Down Sudden Power Loss.
It looks like power supply is oscillating during sudden power off. You may need to check your power supply waveform first.
Our power supply is stable, nothing is oscillating. You can also look at the zoomed in picture here:
Could you measure a full sequence like Figure 6-6. Power Down Sudden Power Loss? What is the other end design of your “shutdown_req_12v” signal? As you can see in P3768_A04 design, shutdown_req is a direct output from module and pulled up to VDD_CVM through a 100k.
I can measure the full sequence.
SHUTDOWN_REQ_12V is directly connected to the #SHUTDOWN_REQ pin of the SoM. The 12V in the name show the maximum signal voltage, which we would use with NX modules. Right now we are using a Nano module and therefore only have 5V.
Here is the measurement you were asking for.
Yellow is the power supply of the module
Purple is POWER_EN
Blue is SHUTDOWN_REQ
Your sequence looks not correct. It should be the power supply (Yellow) drop first and then trigger shutdown_req (Blue). But I can’t see this timing in your sequence. Seems both drop at same time.
No, the sequence is correct. SHUTDOWN_REQ is described as an open-drain signal with a 4k7 pull-up to VDD_VCM. It should perfectly mirror the module power supply until it is pulled down.
However, is it possible that our problem relates to our design not latching POWER_EN to low for a certain time after SHUTDOWN_REQ first asserts? This requirement is not described in the design guide per se, but page number 17 (28 if you are going by the PDF) does have a note about SHUTDOWN_REQ coming from a latch on the module which is cleared by POWER_EN going low.
If yes, could we get some guidance on how long we would be supposed to latch the signal for? It should be quite easy for you, as you have access to the code of the power button supervisor micro-controller.
I mean your waveform should be like below showing. VDD_IN should not sudden drop at beginning if there are enough capacitors, and shutdown_req will sudden drop only when VDD_IN reach the threshold. There is no strict timing request between shutdown_req and power_en.
I am more interested in the grey area show for SHUTDOWN_REQ. For how long do we need to latch POWER_EN and ignore rising edges on SHUTDOWN_REQ?
Any update here? Without clear guidance it will be difficult to make a robust solution
POWER_EN should be held >10ms before VDD_IN drop under 3.0v no matter how long the grey area is.
Meaning we have to hold the signal low until VDD_IN drops below 3V? That is not the same as having a timing requirement.
Hold it > 10ms before VDD_IN = 3V.
Is that what is implemented on the Nvidia development kit? Could you please check? As the code for the supervisor MCU does not seem to be public it is difficult to understand what actually happens in the reference design.
It is requested by whole system. Just make sure your design follow the sequence well.