Nano Shutdown Sequence Questions

We are currently validating the Shutdown sequence of our custom PCBA carrier board with the Jetson Nano Module, There is a timing requirement listed in the product design guide that specifies what the SHUTDOWN_REQ* signal should look like with respect to VDD_IN and POWER_EN :

However, when we probe these three lines on our board, this is what we see on a software shutdown of the Nano:

CH2 (Blue) = VDD_IN | CH3 (Purple) = SHUTDOWN_REQ* | CH4 (Green) = POWER_EN

SHUTDOWN_REQ* comes directly from the Nano module, we don’t have any external pull-ups on that signal so it is only what the Nano Module commands, and when a shutdown is commanded, it asserts low for ~3us rather than a behavior similar to the Power Down timing sequence from the product design guide.

We have questions regarding this shutdown behavior:

  1. Is this expected/safe behavior, and is this sufficient that once we receive this pulse, we set POWER_EN low, or should we see a logic low asserted?

  2. Does our carrier board need to drive this signal low once it is pulsed low by the Nano?

  3. In the NVIDIA Jetson Nano Datasheet Rev 0.7 it specifies a 100k pull-up for the SHUTDOWN_REQ* signal (Figure 1), however in the Jetson Nano Product Design Guide it specifies a 5k pull-up to VDD_IN (Figure 2) which is correct?

  4. Should SHUTDOWN_REQ* be asserted low prior to asserting the PWR_EN signal by the carrier board in other shutdown conditions?

Figure 1 Below:

Figure 2 Below:

Please refer to latest OEM DG in DLC. It has been revised that the pu is 100kohm and your sequence is correct. The shutdown_req will be asserted earlier than power_en as you can see in the on/off logic page in reference schematic.

Thank you! A follow-up, related question:

In the latest documentation, this is the timing sequence for a Sudden Power Loss Event:


  1. Is there a timing requirement for how long SHUTDOWN_REQ* should be asserted between the initial falling edge and the rising edge of the grey block logic state, or is this merely documenting how the Nano behaves

  2. Does that grey block indicate a don’t care state on the SHUTDOWN_REQ* line

  3. Can we assume that after POWER_EN is asserted low any voltage level below the CMOS-logic input high minimum is acceptable (shown below). Eventually we are unable to keep POWER_EN at 0V due to power loss, but our POWER_EN line stays below 0.75*VDD with an RC decay

  1. No such timing is public.
  2. Yes.
  3. The ViL request of module on POWER_EN is 0.4V in max.

Given your response to question 3, is this timing sequence acceptable during a sudden power loss? We are able to assert POWER_EN low for ~20ms immediately after receiving the shutdown request, however after that 20ms due to power loss on our control circuitry we are unable to maintain a logic low, and the voltage rises on POWER_EN to ~2.8V. Is this timing correct?

No, it should be low after power off. You can measure the sequence of dev kit to confirm.