We are currently validating the Shutdown sequence of our custom PCBA carrier board with the Jetson Nano Module, There is a timing requirement listed in the product design guide that specifies what the SHUTDOWN_REQ* signal should look like with respect to VDD_IN and POWER_EN :
However, when we probe these three lines on our board, this is what we see on a software shutdown of the Nano:
CH2 (Blue) = VDD_IN | CH3 (Purple) = SHUTDOWN_REQ* | CH4 (Green) = POWER_EN
SHUTDOWN_REQ* comes directly from the Nano module, we don’t have any external pull-ups on that signal so it is only what the Nano Module commands, and when a shutdown is commanded, it asserts low for ~3us rather than a behavior similar to the Power Down timing sequence from the product design guide.
We have questions regarding this shutdown behavior:
Is this expected/safe behavior, and is this sufficient that once we receive this pulse, we set POWER_EN low, or should we see a logic low asserted?
Does our carrier board need to drive this signal low once it is pulsed low by the Nano?
In the NVIDIA Jetson Nano Datasheet Rev 0.7 it specifies a 100k pull-up for the SHUTDOWN_REQ* signal (Figure 1), however in the Jetson Nano Product Design Guide it specifies a 5k pull-up to VDD_IN (Figure 2) which is correct?
Should SHUTDOWN_REQ* be asserted low prior to asserting the PWR_EN signal by the carrier board in other shutdown conditions?
Figure 1 Below:
Figure 2 Below: