New power sequencing requirements

[cniclaes]

The latest NVidia Jetson Nano Product Design Guide (v2.3 releaser in March 2022 added some constraints about power sequencing. These requirements are clearly bad news for all companies with existing custom carrier board design, knowning that even the Nvidia’s Carrier Board doesn’t fulfill these requirements.

I’ve questions regarding two of them:

1. Figure 5-3: Minimum 400ms delay between VDD_IN and POWER_EN.

Our current design has only 200ms of delay. We sometimes have problem booting the Jetson when the board is completely cold after several hours of OFF state. Could it be linked? What is the purpose of this new requirement?

2. Figure 5-5: Maximum delay of 1.5ms from SHUTDOWN_REQ* to Carrier Board’ 3.3V. This requirement is very difficult to achieve since it means for us to create almost a short-circuit (about 5 ohms) on 3.3V power supply because of all the decoupling capacitors that must be discharged. What is the purpose of this new requirement? What would happen if it’s not fullfilled? On our design, there is no power button, so if a power down is initiated by SHUTDOWN_REQ* (meaning by software), the device will completely shut down and only a disconnect/reconnect of the external power supply will power-up the Jetson again. In this case, must we take this requirement into consideration?

Thanks for help!

[kayccc]

Sorry for the late response, our team will do the investigation and provide suggestions soon. Thanks

[Trumany]

Hi, the 400ms update is for the internal PMIC errata to keep 32khz clock stable enough during power on. For devkit, the rework can be changing R377 = 400k ohm 1% resistor, C280 = 2.2uF 10V 0603. The timing of shutdown is to let carrier board power off earlier than module which can guarantee a correct power down sequence and not affect module pins status during power down.