Hi all,
My question is related about how Tegra or internal PMIC manage the shut down operation.
In the controlled case, reset_out# signal should go low before carrier board start to discharge. In the uncontrolled case, the vin_pwr_bad# signal goes low forcing the carrier board discharge. However, in both cases, we do not understand the internal operation of Jetson, in terms of power consumption. For example, in the case where the Jetson is consuming 7W and a shut down is forced, what procedure or instructions does Jetson execute? How long does it continue consuming 7W?
thanks for your answer, but I think it does not solve my question. Of course I consider this minimum shutdown time, from VIN_PWR_BAD# detected until supply value goes below the critical voltage. As you know, this extra time is supplied from capacitors, but the global capacitor value will depend on how much current the Jetson is consuming. I mean, taking as reference I = C dV/dt, considering dV = 12V-2.9V and dt = 20ms, the capacitor value is directly related to the current through Tegra device, and this current depend of the power consumption after VIN_PWR_BAD#, it it is 7W (as normal working) or 0.5W (idle state) - this is really my question.
When RESET_OUT# generated, the PMC unit in chip will run corresponding process and the load will go low first, and also the capacitors on board can support that for > 20ms.
When you refer to the “capacitors on board”, are you referring to the capacitors on the “TX2 Module” or capacitors on the “Development Kit Carrier Board”? In our design the TX2 VDD_IN is powered by a +6.5V power rail. Given this lower voltage, are the capacitors on board still sufficient to support keeping the voltage on the USB_OTG_ID pin >2.9V for >20ms or do we need additional capacitance on our custom carrier?
What is the average current draw or current profile of the module during this 20ms period?
In the forums, I have seen several users ask what the PMIC is doing during this 20ms period and what the consequences are if this 20ms specification is not achieved. Can you explain what the PMIC is doing during this period? Can you also explain what will happen if this specification is not achieved? Is this to prevent filesystem corruption or is there some other issue that requires this specification of 20ms?
I mean both capacitors on carrier board and module. +6.5V is in the supported range, so no problem on this. You can check the reference schematic to find out how many capacitors used on VDD_IN & VDD_MOD, just following that or placing more capacitors will be ok. Regarding the detail PMIC process, all we can provide are included in the design guide, specification and TRM, if no such info in that, maybe you need to check with vendor, Maxim, the P/N is MAX77620
I understand you can’t say much in regard to the PMIC. Can you at least state what the consequences are if the 20ms specification is not satisfied? For example, is it simply that the filesystem is not properly parked and corruption is risked or are there other affects?
We are within the supported voltage range at +6.5V, but has this 20ms specification been tested on the reference carrier for the “reference schematic” you mention at the lowest end of the supported voltage range for the module? I could see this being tested only at the approximately 19V that the development kit actually operates at.
Is there some log file, or other indication that I can check after the fact, to show that the system had a controlled shutdown due to low voltage, and whether the >20ms target was attained? Basically I want to query the PMIC history after reboot.