Really I don’t understand controlled power-down of figure 4:
How RESET_OUT# is pulled down, if it is connected to the POWER GOOD pin of the 1.8V POL of the board, and this is still active, according to the figure 4. This POL is enabled from 3V3 POL, and the sequence starts with CARRIER_PWR_ON --> 5V --> 3V3 --> 1V8?
I understand CARRIER_PWR_ON as a POWER GOOD signal of the internal PMIC of the Jetson TX2, so when the internal voltages are stabilized, CARRIER_PWR_ON is active. The OEM confirms this idea. How CARRIER_PWR_ON is pulled down, if input voltage is active and RESET_IN# signal is not used? Figure 1 of OEM does not show signals between TEGRA and Power Subsystem.
Why there is a typical time between RESET_OUT# and CARRIER_PWR_ON, if both signals are independent of each other?