Controlled power down and carrier power on signal


Really I don’t understand controlled power-down of figure 4:

  • How RESET_OUT# is pulled down, if it is connected to the POWER GOOD pin of the 1.8V POL of the board, and this is still active, according to the figure 4. This POL is enabled from 3V3 POL, and the sequence starts with CARRIER_PWR_ON --> 5V --> 3V3 --> 1V8?

  • I understand CARRIER_PWR_ON as a POWER GOOD signal of the internal PMIC of the Jetson TX2, so when the internal voltages are stabilized, CARRIER_PWR_ON is active. The OEM confirms this idea. How CARRIER_PWR_ON is pulled down, if input voltage is active and RESET_IN# signal is not used? Figure 1 of OEM does not show signals between TEGRA and Power Subsystem.

  • Why there is a typical time between RESET_OUT# and CARRIER_PWR_ON, if both signals are independent of each other?


Hi, RESET_OUT# is pulled down by RESET_IN# which is triggered by power down process (such as power button pressing), and CARRIER_PWR_ON is pulled down then in module.

Hi Trumany,

if the power button is pressed, the RESET_IN# signal is asserted and then, through the diode, RESET_OUT# is also asserted (figure 1 of OEM datasheet), causing a reset of the PMIC, eMMC and Tegra. My question is regarding to the shutdown request by software, which also causes the RESET_OUT# to change to low state. I mis how the sequence is!! From Jetson TX2 System-On-Module datasheet, pag. 20, says:

On receiving a Shutdown request the Jetson TX2 will assert the RESET_OUT# signal, allowing the carrier board to put any
components into a known state. The CARRIER_PWR_ON signal will then be de-asserted to indicate to the carrier board to
power down. The carrier board must disable its power at this point; the module will then disable its power and shut down

Then, I understand that Tegra forces internally the assertion of RESET_OUT# and then, with an internal signal to PMIC (what signal is?), it indicates to the PMIC module to set in low state CARRIER_PWR_ON signal, starting the carrier board powers shutdown (VDD_SYS voltages). I mean, both signal RESET_OUT# and CARRIER_PWR_ON, are driven low by the Jetson TX2 SOM, not the carrier board.

We have also implemented the autopower-on functionality through tying the CHARGER_PRSNT# to GND. In the case of controlled shutdown, both shutdown request or pressing the power button, the system will shut down. In the no autopower-on case, the system is restarting by pressing again the power button. However, for the autopower-on case, there is not any specification. Is it also necessary to press the power button, or there is other different sequence?


The power down sequence request by software is also a kind of controlled case, so it is as showing in figure 4.

And yes, it is necessary to press power button in auto power on case.

Hi Trumany,

with an oscilloscope we have seen that RESET_IN# and RESET_OUT# fall down at the same time, after we order a shutdown command. So in the controlled case, TEGRA chip is the responsable to assert the RESET_OUT# signal and, in somehow, the RESET_IN# is also asserted by the PMIC module. Is this true?

So as summary, RESET_OUT# is controlled by the carrier board during power on (the power good of 1.8V DC converter keeps low this signal until the voltage is stable) and controlled by the Tegra during power off, as described in this thread.


Almost like you said. Tegra is to notice PMIC to reset and so RESET_IN# is asserted by PMIC and then the RESET_OUT# is pulled low by RESET_IN# (thru a diode).