TX2 module: power down sequencing CARRIER_PWR_ON does not drop following RESET_OUT active (low)

Hello,

We’re developing a carrier board for use with the Jetson TX2. We have been designing according to the Jetson_TX2_OEM_Product_DesignGuide_v20170501.pdf. We have confirmed the power-up sequence in Figure 3 and were confirming the controlled power down sequence in Figure 4. We discovered that asserting RESET_OUT active (low) does not result in the TX2 module setting CARRIER_PWR_ON module low as indicated. We confirmed this behaviour on the devkit by bridging J8 while scoping U31 pin 1 (the trace that goes to R507). What is the proper power down sequence and expected outputs from the tx2 module?

Thanks.

Hi dthompson,

The figure 4 is the power down sequence of whole system in controlled case, that does not indicate the sequence of active RESET_OUT# only. In fact, if the RESET_OUT# is enabled from carrier board, that will only reset Tegra & eMMC, not PMIC, and so the CARRIER_PWR_ON will not be pulled low. You can see the corresponding power down sequence by press RESET button which will active the RESET_IN# and so reset PMIC, Tegra & eMMC.

I think the confusion was in that RESET_OUT# is bidirectional. We were under the impression that the carrier was able to initiate the controlled shutdown. The TX2 module specification guide wording is much clearer than the OEM product guide.

Thanks!

" You can see the corresponding power down sequence by press RESET button which will active the RESET_IN# and so reset PMIC, Tegra & eMMC."

Can somebody show this sequence? I am also having trouble getting CARRIER_PWR_ON to go low, whether I use RESET_IN# or RESET_OUT#. My power up sequence appears to work fine.

Thanks!

Tim

Hi ttsai, you mean can’t see any drop on CARRIER_PWR_ON even when press RESET button? That’s weird, as the RESET signal will trigger PMIC reset and the pull-up voltage of CARRIER_PWR_ON will have a drop. Has any other connection effect it?

Hi Trumany,

related to this post:

[i]Hi dthompson,

The figure 4 is the power down sequence of whole system in controlled case, that does not indicate the sequence of active RESET_OUT# only. In fact, if the RESET_OUT# is enabled from carrier board, that will only reset Tegra & eMMC, not PMIC, and so the CARRIER_PWR_ON will not be pulled low. You can see the corresponding power down sequence by press RESET button which will active the RESET_IN# and so reset PMIC, Tegra & eMMC.[/i]

Really I don’t understand controlled power-down of figure 4:

  • How RESET_OUT# is pulled down, if it is connected to the POWER GOOD pin of the 1.8V POL of the board, and this is still active, according to the figure 4. This POL is enabled from 3V3 POL, and the sequence starts with CARRIER_PWR_ON --> 5V --> 3V3 --> 1V8?

  • I understand CARRIER_PWR_ON as a POWER GOOD signal of the internal PMIC of the Jetson TX2, so when the internal voltages are stabilized, CARRIER_PWR_ON is active. The OEM confirms this idea. How CARRIER_PWR_ON is pulled down, if input voltage is active and RESET_IN# signal is not used? Figure 1 of OEM does not show signals between TEGRA and Power Subsystem.

  • Why there is a typical time between RESET_OUT# and CARRIER_PWR_ON, if both signals are independent of each other?

Thanks!