[HW] Power Sequence & Reset pins


I have some doubts about TX1 Hardware.

First for the resets (RESET_IN# & RESET_OUT#) :
In the document “JetsonTX1_OEM_Product_DesignGuide-1000010-13.pdf” I’ve noticed some incoherences :
*page 15 :
RESET_IN# is said to be on A46…is on A47 in the Jetson TX1 schematic (“P2597_B02_Concept_schematics.pdf” page 4)
RESET_OUT# is said to be on A47…is on A46 in the Jetson TX1 schematic (“P2597_B02_Concept_schematics.pdf” page 4)
same inversion for the chart below the synoptic.
*page 53 (with JTAG explanation) :
the pinout of them seems to be the right one here… Can somebody from NVIDIA confirm ?

Second question about them : which one is wired to the TX1 and which one is wired to the MAX77620 ?
If we invert RESET_IN# and RESET_OUT# nets on page 15 (to have the right pinout) it leads to a system with RESET_IN# on PMIC and RESET_OUT# on EMMC + TEGRA (maybe not represented devices like SPI Flash or EEPROM too ???)
If we look RESET_IN# and RESET_OUT# nets on page 53 we have a system with RESET_IN# on Tegra X1 and RESET_OUT# on PMIC.

Last question about resets is : can someone confirm that the diode between those two pins aim is to assert (active low) RESET_OUT# when RESET_IN# is asserted (active low) from Carrier board ?

For the power sequence p17 in the OEM, somebody knows the timing between all steps ? Or at least their order of magnitude (ms ? sec ?).
In the power-down sequence what event or timing is putting Jetson TX1 System Power off from the Carrier Board System Power turned down ?

Have a nice day,

Here’s some info about the sequence timing:

    Timing between steps #1 and 2 of the power sequencing
  • waiting one second (from VIN_PWR_BAD# to the POWER_BTN# press) should be sufficient
    Is there a minimum pulse width on the button signal?
  • It looks for a falling edge and there is a debounce time of 36ms max.
  • After power on, if the POWER_BTN# is held low for ~10sec it will cause a HW shutdown (less than that is a SW interrupt and SW shutdown)
    What actually triggers the power-on sequence?
  • The falling edge of POWER_BTN#
    What happens if the Power button is held low when the VDD_IN is applied?
  • It doesn’t power on, the PMIC needs to see the falling edge.

Thanks for raising the question, we are confirming what is correct and the proper RESET_* behavior.

Thank you Dusty for your answer.

For the reset, I’m more interested in knowing which pin is on the PMIC and which one is on the TX1 than the pinout (Jetson always tells the truth).

For the power off sequence I really want to know what information the Carrier Board brings to initiate the Tegra X1 core power-off sequence (from step 3 to step 5) ? Maybe is it another timer ?

One other question about this sequence : how long should we maintain the VDD_IN_ & VIN_PWR_BAD# high after the peripherals supplies (voltage Carrier Board System Power) are going low ?

Best regards,

OK, confirmed that RESET_OUT# is on pin A46, and RESET_IN# on pin A47.

RESET_IN# goes directly to the PMIC NRST_IO pin, which is basically bidirectional. RESET_IN comes from several sources on the carrier board including the reset button, debug connector or JTAG connector.

RESET_OUT# comes from the PMIC on the other side of a diode. The diode is there to keep the PMIC from being reset when PMIC_SYS_RST* is driven low to reset Tegra X1 to enter boundary scan mode (can be done by jumpering J8 on the reference carrier board).

Hello Dusty,

Thank you very much, very helpful :).

One last thing (pin :p) about reset… maybe it is out of your knowledge… but does it suitable to use JTAG ARM-20 probe from Lauterbach with JTAG_TRST_L unconnected and only pulled up on the carrier board ?

Once again thanks,

Hi alejuventino,

That would be fine from a JTAG perspective (nTRST is optional) – but it would depend if the Lauterbach software
can perform a TAP reset in some other means (for instance clocking TCK while TMS is held high will reset the JTAG state machine).

Since the TX1 uses an ARM7TDMI and an ARM CoreSight DAP, nTRST really only has a major effect on the JTAG state
machine and not the internal debug logic. This is documented in the “ARM Debug Interface Architecture Specification ADIv5.0 to ADIv5.2”, in section 3.23:

The DBGTRSTn signal only resets the DBGTAP state machine and Instruction Register. DBGTRSTn asynchronously takes the DBGTAPSM to the Test-Logic-Reset state. As shown in Figure 3-3 on page 3-72, the Test-Logic-Reset state can also be entered synchronously from any state by a sequence of five TCK cycles with DBGTMS HIGH. However, depending on the initial state of the DBGTAPSM, this might take the state machine through one of the Update states, with the resulting side effects.

Usually the side effects are somewhat minor if you’re connecting after powering up the board and have no
previous JTAG state – it’s usually less desirable if you’re resetting the board between debug sessions.

Thank you very much nekoxp ;)


I also wanted an answer to alejuventino’s question:

" For the power off sequence I really want to know what information the Carrier Board brings to initiate the Tegra X1 core power-off sequence (from step 3 to step 5) ? Maybe is it another timer ? "

I’m looking at the discharge FETs, which are there to meet some implicit timing requirement, but I don’t know what that is and therefore can’t guarantee I’ll meet it given the caps etc on my board.


RESET_IN# (A47) , that is connected to RESET button on carrier board, will deliver a full system reset including the PMIC.
RESET_OUT# (A46) is only to reset TX1.