I have some doubts about TX1 Hardware.
First for the resets (RESET_IN# & RESET_OUT#) :
In the document “JetsonTX1_OEM_Product_DesignGuide-1000010-13.pdf” I’ve noticed some incoherences :
*page 15 :
RESET_IN# is said to be on A46…is on A47 in the Jetson TX1 schematic (“P2597_B02_Concept_schematics.pdf” page 4)
RESET_OUT# is said to be on A47…is on A46 in the Jetson TX1 schematic (“P2597_B02_Concept_schematics.pdf” page 4)
same inversion for the chart below the synoptic.
*page 53 (with JTAG explanation) :
the pinout of them seems to be the right one here… Can somebody from NVIDIA confirm ?
Second question about them : which one is wired to the TX1 and which one is wired to the MAX77620 ?
If we invert RESET_IN# and RESET_OUT# nets on page 15 (to have the right pinout) it leads to a system with RESET_IN# on PMIC and RESET_OUT# on EMMC + TEGRA (maybe not represented devices like SPI Flash or EEPROM too ???)
If we look RESET_IN# and RESET_OUT# nets on page 53 we have a system with RESET_IN# on Tegra X1 and RESET_OUT# on PMIC.
Last question about resets is : can someone confirm that the diode between those two pins aim is to assert (active low) RESET_OUT# when RESET_IN# is asserted (active low) from Carrier board ?
For the power sequence p17 in the OEM, somebody knows the timing between all steps ? Or at least their order of magnitude (ms ? sec ?).
In the power-down sequence what event or timing is putting Jetson TX1 System Power off from the Carrier Board System Power turned down ?
Have a nice day,