We are trying to design a carrier board with an external microcontroller that will act as a Power Management IC and doing other low-level functions. Because we are adding the microcontroller, many of the circuits from the reference design cannot be used outright.
The Jetson Product Design Guide, in the “Power” section, shows the following power sequence:
However nowhere else in the Datasheet or Product Design Guide does it mention a timing parameter for the POWER_EN being latched low, and this parameter seems somewhat ambiguous. Does this mean that the POWER_EN must be latched within that 10us window? Why is this requirement necessary? Is there a place to find more information on the specifics of the Power sequencing procedure?
Does this mean that the POWER_EN must be latched within that 10us window?
Yes, that’s what that timing diagram indicates.
Why is this requirement necessary?
SHUTDOWN_REQ* signals in response to software, thermal, or power-bad. Software probably isn’t too important, but I suspect the other two could cause hardware damage if not responded to quickly.
Also there is probably a maximum time that SHUTDOWN_REQ* may be asserted, so if you don’t service it, you might miss it.
I understand that the timing is necessary given that it says so in the datasheet, but I am still unclear as to why. What is the reasoning for this timing requirement? I have looked at the schematic, and while I understand what that circuit is doing, because we are using a microcontroller to run the power and main control of our system, much of the circuitry doesn’t necessarily work for our application.
I did some scope captures on the P3449 Board, checking power down timings on a sudden power loss event. The following scope traces are:
CH1(Yellow): Power Button Signal
CH2(Light Blue): POWER_EN
CH3(Pink): SYS_RESET
CH4(Dark Blue): SHUTDOWN_REQ*
As you can see the P3449 board does NOT follow the requirements shown in the Datasheet or Product Design Guide. Is it better to follow the Datasheet and Product Design Guide or the reference schematic? What is the length of time that SHUTDOWN_REQ will actually stay low? Also, in a slightly different vein, is the SYS_RESET line going low a function of the sudden power loss or the POWER_EN signal?
Just following up, is there any more information on the power sequencing requirements for the Jetson Nano and how they differ from the reference design?
Hi, The <10us is somewhat erroneous, will be corrected in DG. Our validation data shows it can range from 17us to 22us which matches with the users. Thanks.
This timing requirement doesn’t make any sense. What happens if we have a design that lowers POWER_EN only 10us after the SHUTDOWN_REQ? What happens if POWER_EN is lowered at 30us? It’s still very unclear as to why this requirement exists, and the lack of clarity makes it difficult to design around.
Based on the latest timing information you gave it seems like the reference design has a glaring error, where this power enable circuit dropped the POWER_EN line just before the edge of the window. Slight changes in a capacitor or resistor could push this timing outside of the range you mentioned in the last message.
This timing is for the design using discrete logic same as devkit. If customers are using this discrete logic then the delay is about 20us. If they are implementing MCU solution then check 5V is stable before asserting POWER_EN and turn off POWER_EN as soon as SHUTDOWN_REQ* is asserted.
Turn off module ASAP before 5V drains to 3V where PMIC UVLO is reached. Shutdown Tegra properly and not cut out power. So essentially it depends on customers, how much bulk caps they have on 5V and at max load how much time do they have to service POWER_EN to ensure proper power down sequence before 5V reaches 3V.
