The design guidance requires that when the POWER_EN drops after the 10ms, the VDD_IN (5V) is allowed to drop to 3V, which is easy to achieve on the P3448 because it is directly powered by a 5V power supply.
When the power supply of my system is 12V, this requirement will be difficult to meet, because most 12V-> 5V DCDC converter have discharge function, which means that when the power is off, converter will take the initiative to discharge the power on 5V quickly, so that it can not meet the requirements of the design guidance.
So I want to make sure that this item must be satisfied, for example, whether 4ms is acceptable at this time?
Yes, T>10ms is must.
Do you have any good suggestions for 12V input systems, because most of the 12V-> 5V converter have discharge function, which will make it impossible to meet this requirement?
No, we don’t have such recommendation.
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