Xavier NX Power Down Sequence

Hi,

I got some questions about the Power-Down Sequence.

  • On Power-Down after SHUTDOWN-REQ* is asserted low, I need to deassert POWER_EN as soon as possible with a maximum possible delay of 10us.
    What will happen if I am not able to deassert POWER_EN in the given time?

  • In case of a Sudden Power Loss Shutdown I must guarantee that for 10ms VDD_IN doesn’t fall below 3V.
    What does the NX do in that given time?
    What will happen if I can’t maintain the 3V on VDD_IN?
    Is the Power Consumption reduced in those 10ms?

  • After POWER_EN is deasserted the SYS_RESET* Signal will be asserted by the module.
    Does that always happen?
    What is the delay between “POWER_EN is deasserted” and “SYS_RESET* is asserted”.

Thank you in advance.

hello tjamboeck,

please also refer to Jetson Xavier NX Product Design Guide, check chapter-5 for the details of power sequence.
thanks

Hello JerryChang,

Thank you for your fast response.
Unfortunately I already looked it up in the Product Design Guide and the Datasheet. Those documents didn’t contain the answers to my questions.

The 10us delay is request of system design, should be followed well.

System is running power down process during the 10ms. It should be followed well too. The power consumption is reduced in that.

The delay between POWER_EN deserted and SYS_RESET is controlled by PMIC which is not so strict.

Hello Trumany,

Is there an estimated power consumption during the 10ms power down process?

Because SYS_RESET is set by the PMIC, is it possible to shut down the external power supply (1V8, 3V3…) with the falling edge of SYS_RESET instead of POWER_EN?

thank you in advance

No such power consumption data.

The carrier board power supply is controlled by SYS_RESET as you can see in Figure 4-1. System Power and Control Block Diagram

Hi Trumany,

Thank you for you answer. I still got one more question I want to ask you.

I did some Measurements on my own to determine the exact delay between POWER_EN and SYS_RESET. As you can see in the following picture, there is a delay of 1ms.

During that time the carrier-board power supplies and peripherals are still running. So there is a higher power consumption which would lead to larger capacitors to meet the required 10ms of VDD_IN over 3V, especially in the case of a Power Loss shutdown.

Now to my question. Is it possible to shutdown the carrier-board power supplies and peripherals with POWER_EN instead of the delayed SYS_RESET? This measure would mean that I could use smaller capacitors.

Then what about the power on sequence? Can that guarantee carrier power on later than module?

Don’t suggest to do that.

During the power on sequence I am using SYS_RESET to enable the carrier power as shown in the datasheet. In case of Power down or Power Loss I am considering using Power_EN instead of SYS_RESET, due to the facts I already mentioned.

Is there more detailed information about, why it is necessary to use SYS_RESET to power down the carrier power?
What are the side effects if I use POWER_EN for shutting down the carrier power?

What you mentioned is not validated and we don’t recommend. You can try that, the key point is to let carrier board power off earlier than module.