Shutdown/Power Down Timing Violation

Continuing the discussion from SHUTDOWN_REQ# question:
The Xavier NX Design guide (Fig. 5-6) shows T>10ms time required for the module to properly shut down after Power_EN de-assertion. I have a couple of questions about this:

+The last paragraph in the “SHUTDOWN_REQ*” Section on Design Guide p.13 seems to imply 4-5ms needed to shut down properly. This appears to be in disagreement with the >10ms timing shown in Fig. 5-6. Which value should be used?

+Assuming it can be guaranteed that there will be no back feed to the Xavier NX module from the carrier board power supplies, what is the worst-case outcome of not providing 10ms for proper shutdown sequence? If the extent of the problem is a corruption of boot memory, could that be restored via a recovery bootup from the USB port and subsequent restoration of boot memory?

Thank you.

  1. That’s not conflict. 10ms is from POWER_EN de-assertion to dropping to 3.0V. 4-5ms is PMIC power down timing.

  2. As below said in DG, the 10ms is for safety.

To satisfy the power down sequencing requirement and prevent unwanted back drive from the carrier board to the module, the following must be true:
 The carrier board 3.3V power supply that powers any module I/O must be off within 1.5 ms of SYS_RESET* assertion.
 The 1.8V power supply that powers any module I/O must be off within 4 ms.
 The power rails should be fully discharged before attempting to power back up.

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