On a custom carrier Board, we designed some logic to delay POWER_EN (650ms) from Module Power. We had issues if a short power loss occurs, the board was not starting again, if the POWER_EN comes back too fast.
Now we have the Problem, if that delay is too long, the Board is not starting from cold conditions.
I found no requirement, that there is a maximum time when module power is stable and POWER_EN must go high. Is there any maximum time?
The Interface supplies (1V8, 3V3) are enabled by the RESET Signal of the TX2 NX.
I know these the design guide and board meet these requirements!
As I described, VIN (5V) is stable and the SYS_Reset is not release, if the POWER_EN rises later than 650ms after VIN is stable. In the Design Guide is no maximum Time specified.
Please check if there is any back drive on the Strap pins of the module from the carrier board within this 650ms time window before the module is powered on. When do you power the carrier board circuits? Please check the power up sequence signals and compare them against the design guide.
The carrier board supplies (5V,3V3,1V8) are enabled by the SOM-RESET signal. So they stay disabled.
I see no mismatch with the power up sequence in the design guide.
SHUTDOWN_REQ goes high with the 5V SOM. 650ms later POWER_EN goes high but SYS_RESET stays low. If POWER_EN goes high 400ms after SHUTDOWN_REQ everything works fine.
we do not use the button MCU. Our System is starting automatically with the Main Power Supply, and we implemented some logic to keep the timings. In our proucts every programmabel Part is causing a lot of afford in Software Management (Produciton, Field Updates..).
Regarding the Strap Pins there are the following circuits:
Pin 99: goes to a Level shifter LSF0204. The level shifter is not powered
PIN103: not connected
PIN203: Goes to the base of a npn transistor and has a 10k pull down
PIN214: goes to a Button and has a 100p Cap to GND
At the time we designed that Board, the design guide was at revision1.1 and there was no 400ms specified. We were one of the users to find out that this time is needed. So we implemented some margin to be safe regarding tolerances, and the typical time of 650ms was the result.
Power_EN is driven by 74LVC logic. So risetime should be no problem. I have only shot with 100ms/div. So it’s not usable to measure the rise time exactly.
If not using power button MCU, could you try below circuitry from our earlier carrier board design for Jetson Nano and see if it works for you Jetson Nano Developer Kit Carrier Board Design Files (P3449 B01)Log in | NVIDIA Developer
