Xavier carrier board design questions - Power up/down sequence + power button

Hi Guys,
Trying to find answers in all documents but could not find would love for some urgent assisting here:

  1. Power up/down sequence (DS V1.2 chapter 2.2)
    1.1 regarding power-up/down sequence requirement - module relative to the carrier (module should power up first and power down last):
    1.1.1 is this required for latchup protection?
    1.1.2 does this requirement apply also for the PCIe endpoint? - i have no control on the power of the PCI endpoint power…
    1.1.2 does this requirement apply also for the USB/HDMI device? - should the 5V power on the USB/HDMI connector be powered up/down together with the other carrier rails on a power-up/down sequence?
    (i.e. on a CARRIER_POWER_ON assertion/de-assertion)
    1.2 the PU sequence of the DS (figure 3) shows that the SYS_RESET_N is deasserted by the GPU at the end of the PU sequence,
    can you please supply a timing diagram for this event? (is it a fixed value after CARRIER_POWER_ON signal assertion event?)
    1.3 the PD sequence of the DS (figure 4) shows that VDDIN_BAD is asserted low together with SYS_RESET_N.
    does this figure show a power down sequence due to a fault in the VIN voltages?
    according to figure 4, the module is powered down first and only then the carrier power rails , this is in contradiction to the text description of section 2.2.2
    that specifically mentions that the CARRIER_POWER_ON is deasserted first and only then the module disables its power(i suppose that this occurs only when the carrier
    power controller de-asserts the MODULE_POWER_ON signal, right?)
    please advise on this contradiction.

  2. PWR_BTN_N:
    this signal enters the SOC ,what is it needed for? (What is the required timing of assertion ?)
    we don’t intend to put the GPU into sleep, In this case, can I leave the PWR_BTN_N floating?

figure 3 in DS(V1.2) for power-up sequence shows that the power button is pressed after HV&MV&PWR_BAD are all in their
required state, this contradicts figure 5-2 (OEM DG V2.2) – there it is pressed BEFORE.
Please advise – which is correct?
** there shall be no button in our design , can we just initiate power ON event to the module by asserting only MODULE_PWR_ON signal to module ?

4.VCC_RTC not used in my design – what to do with this pin? leave unconnected?

5.USB(2.0 only in our design):
USB0 - shall be used for recovery mode only.
should I disconnect the USB connector from power in our carrier design and connect only GND+diff data pair?

The module should be power on first and power down last especially for the IO block that be shared by module and carrier.

For power up/down sequence, please refer to product design guide for detail info as it is rough in datasheet. The timing is not so critical as you can see in the figures. There are several different sequence such as power-off to power-on (power button case) and etc.

VCC_RTC can be unconnected.

VBUS of USB0 should follow the example “USB 3.1 USB Micro AB Connection Example” to connect to GPIO10.

I am using the Schematic_Checklist excel (version 1.1 from 20.7.20)

In the USB_PEX_UFS tab, it is mentioned (row 12) to connect GPIO10 with a 100k PU to vdd_1v8 , in the other hand , you guided us to follow “USB 3.1 USB Micro AB Connection Example” for VBUS of USB0 (see mail below).

In that example, the connection to GPIO10 is 3.3v.

Is it for USB3.1 and USB recovery on same port?

It is 3.3v for the pin.

Other 2 questions:

  1. The signal OVERTEMP_N (pin L52) is mentioned as an input pin (DG 2.2 , TABLE 5-1) , however, it seems connected as an output
    At the reference schematics (it inputs U83 and gate , page 6).

The pinout table in the D.S (V1.2) sets the voltage level of the PEX_xx_RST_N pins to be 1.8v

(e.g. PIN D10,H10…etc.)

However, the PCIe standard is 3.3v and the schematics of the carrier + the D.G(2.2) page at figure 7-4 shows that the reset signal

Is connected to 3.3v PU.

Pls advise.


  1. OVERTEMP_N is an INPUT signal to Tegra chip. The signal direction in schematic will be corrected

  2. The pins are 1.8v CMOS but 3.3v tolerance, and their PU is 3.3v in module.

Thanks!! other issues I had with HDMI jitter information:

I need the maximum jitter value at the HDMI outputs of the device

Preferably I would like to have also the **mask of the output waveform of the device on the HDMI outputs
i have reviewed the HDMI tuning guide and i’m missing some information:
(1) The eye mask “dimensions” (i.e., width & height) are not expressed explicitly, and one cannot decipher them from the diagram at Figures 1 & 2 .
(2) While one can see and understand that the amplitude (swing) of the clock pair is to be app. 1000mV, there’s no mention of the expected maximum jitter, which determines the “width” of the eye (and the mask) and which is a parameter of the driver, not something the user can control, and therefore should be defined at the device specifications either as a “maximum jitter” parameter or as part of the required mask at the outputs of the device
(3) It seems the document deals with the clock pair only; there’s no mention of data pairs

can you please help me with that?


The Tuning and Compliance Guide AN is all we can provide. It is based on HDMI specification, required equipment and software. The eye diagram test spec should be included in the software of oscilloscope. You can read the manual or check the settings of it to get more detail info.