SYS_RESET* Functionality During Power Down


I am developing carrier board for xavier nx.
I have questions on the SYS_RESET* handling
As datasheet requests (Xavier NX 1.6v) the sys_reset is used to power up the carrier board. It is connected as input to the carrier sequencer. If the sys_reset is low then carrier power rails are off.

When the carrier is up (normal state) and I want to drive the sys_reset for NX programing I will have the following situation.

  • The user drives the sys_reset low
  • The NX receives sys_reset low and on the same time all the carrier board power rails turn off (because this signal is input to the sequencer)
  • The module does full power cycle
  • The logic that drive the sys_reset* is longer functional because of power drop

My questions are:

  • For NX programming should i use the SYS_RESET* indication or should i drive the power enable off and then on?
  • How fast does the module trigger the SYS_RESET* low assertion
  • Should I make delay on the SYS_RESET* so the sequencer will not drop all the carrier power and the NX will have the time to detect the assertion
  • What is the recommeded way to enter module to SW programing state?


hello tal.roey,

please check Jetson Xavier NX Product Design Guide, please refer to [5.1 Power Supply and Sequencing] for reference.

I am addressing you because the datasheet is not clear

please refer to power up/down sequence.

please check the documentation. there’s suggest delay in the diagram.

I’m not fully understand this, may I know what’s the actual use-case here.

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