TX2 NX uartb HW flow control not work

Hi ,

I’m using TX2-NX SOM with customize designed board, UARTB flow control (PIN103/105) doesn’t work.
sudo minicom /dev/ttyTHS1 (set with hw flow control), PIN 103/105 not connect,
When RTS/CTS not connect, data input/output shouldn’t success, but it does transfer R/W successful.

if change to NX SOM, hw flow control on UARTB not work ether.

Do anyone know how to fix this issue ??

The TX/RX for UARTB is pin 99/101. Do you have further use-case to use pin 103/105?


What configuration have you done? And I am not sure why you used the case “RTS/CTS” not connected to prove something not work.

Have you checked the case which has bot pins connected?

Hi DaneLLL,
Yes, we want to use CTS/RTS pin for serial hw flow control.
But it doesn’t work .


H WayneWWW,

Didn’t do any config for uartb. (using default image)
Testing 4-line uart with full function(RX/TX/RTS/CTS), we expect data will not transfer if RTS/CTS are not connect to CTS/RTS.

The condition is ,only RX/TX connect to TX/RX , and hw flow control enabled. ===> data can read/write from/to another UART.
This means RTS/CTS function not work .

Please apply this patch and try again:
Uart flow control on Jetson Nano - #9 by JerryChang

The driver is same for TX1 and TX2 so this patch is required.

Hi DaneLLL,

We did patch the code before posting this issue, still not work.
And, we also have another 4-line uart on uartc (ttyTHS2) , without patch code , it works fine.
only uartb abnormal.

Since uartc works in your set up and would like to get more information. By default UART3_RTS and UART3_CTS are initialized as GPIO. Do you modify pinmux spreadsheet to initialize the pins to UC3_RTS and UC3_CTS functions?

Hi DaneLLL,

Yes, we do set pinmux for all uart pin. also check Linux_for_tegra mb1 pinmux setting

Bank: 1 Reg: 0x0c302008 Val: 0x00000458 → uart3_cts_pw5
Bank: 1 Reg: 0x0c302010 Val: 0x00000408 → uart3_rts_pw4
Bank: 1 Reg: 0x0c302018 Val: 0x00000454 → uart3_rx_pw3
Bank: 1 Reg: 0x0c302020 Val: 0x00000400 → uart3_tx_pw2

Bank: 0 Reg: 0x0243d020 Val: 0x00000400 → uart2_tx_px0
Bank: 0 Reg: 0x0243d028 Val: 0x00000454 → uart2_rx_px1
Bank: 0 Reg: 0x0243d030 Val: 0x00000408 → uart2_rts_px2
Bank: 0 Reg: 0x0243d038 Val: 0x00000458 → uart2_cts_px3

grep X /sys/kernel/debug/tegra_gpio

X:0 0x0 0x0 0x0 0x1 0x0 0x0
X:1 0x0 0x0 0x0 0x1 0x0 0x0
X:2 0x0 0x0 0x0 0x1 0x0 0x0
X:3 0x0 0x0 0x0 0x1 0x0 0x0

grep W /sys/kernel/debug/tegra-gpio-aon

W:2 0x0 0x0 0x0 0x1 0x0 0x0
W:3 0x0 0x0 0x0 0x1 0x0 0x0
W:4 0x0 0x0 0x0 0x1 0x0 0x0
W:5 0x0 0x0 0x0 0x1 0x0 0x0

Hi ,

Is it possible that uartb hw flow control behavior is not as expect because additional logic on pin103???

We are checking with internal team. See if there is further idea about this. Will update.

We have checked and it may be due to status of pin 103. The pin is used for SoC strap and it may be tied to a constant value, affecting the functionality. For further check, please configure the pin to gpio, toggle the GPIO and then observe whether the signal is correct.

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