The TX2 SPIdev driver seems to be receiving data that is right shifted (>>) by one bit. I have verified that the DUT is sending correct data on an oscilloscope. The output of the decoded transfer reads:
0x70 0x00 0x0D 0x30 0x73 0xBA …
while the buffer dump read from spidev reads the following
0x38 0x00 0x06 0x18 0x39 0xdc …
performing a binary comparison on the two data sequences it becomes apparent that the spidev data is shifted by one bit, performing a software left shift (<<) corrects the error but the last bit is lost in the data transfer. I have also tested using a kernel module and spi_read() with the same outcome.
I am using spi mode 3 with SPI_CPOL and SPI_CPHA bits set. The scope decode is set to sample on CLK rising edge with MISO “1” being active high to match mode 3.
For reference when the test code was tested on a raspberry pi 3B it produced correct results.
Is this a known issue and is there a fix available?