Uboot support for pcie access

Robotics & Edge Computing Jetson & Embedded Systems Jetson TX2
1

Hi,
Is there any configurations that can enable uboot support for pci/pcie memory space access?

Currently uboot can only access pci config data:

Tegra186 (P2771-0000-500) # pci next b 0xc0000000
No such device
Tegra186 (P2771-0000-500) # pci regions
Scanning PCI devices on bus 0
BusDevFun VendorId DeviceId Device Class Sub-Class

00.01.00 0x10de 0x10e5 Bridge device 0x04
Tegra186 (P2771-0000-500) #

2

Well, if the device connected has a driver available in u-boot, then, that driver should be able to access the device’s memory space.
Is your question about accessing the memory space without really having a driver in u-boot for the device being connected?

3

The FPGA is connected with pcie x4 lane and would like to read its version memory.
Issued ‘pci enum’ and enabled debug message. pci_tegra is able to find memory controller. But I don’t where the FPGA memory space is located at.

------------------- trace ---------------------------
Tegra186 (P2771-0000-500) # pci enum
2 !!! do_pci
3 !!! pci_init
pci_uclass_pre_probe, bus=0/pcie-controller@10003000, parent=root_driver
decode_regions: len=42, cells_per_record=7
decode_regions: region 0, pci_addr=10000000, addr=10000000, size=1000, space_code=2

  • type=0, pos=0
    decode_regions: region 1, pci_addr=10001000, addr=10001000, size=1000, space_code=2
  • type=0, pos=0
    decode_regions: region 1, pci_addr=10004000, addr=10004000, size=1000, space_code=2
  • type=0, pos=0
    decode_regions: region 1, pci_addr=0, addr=50000000, size=10000, space_code=1
  • type=1, pos=1
    decode_regions: region 2, pci_addr=50100000, addr=50100000, size=7f00000, space_code=2
  • type=0, pos=0
    decode_regions: region 2, pci_addr=58000000, addr=58000000, size=28000000, space_code=2
  • type=8, pos=2
    tegra_pcie_board_init: Set LDO7 for PEX power to 1.05V

tegra-pcie: x4 x1 configuration
tegra-pcie: probing port 0, using 4 lanes
pci_uclass_post_probe: probing bus 0
pci_bind_bus_devices: bus 0/pcie-controller@10003000: found device 1, function 0
pci_find_and_bind_driver: Searching for driver: vendor=10de, device=10e5
pci_find_and_bind_driver: No match found: bound generic driver instead
pci_auto_config_devices: start
pci_auto_config_devices: device pci_0:1.0
dm_pci_hose_probe_bus
pci_get_bus_max: ret=0
dm_pci_hose_probe_bus: bus = 1/pci_0:1.0
pci_uclass_pre_probe, bus=1/pci_0:1.0, parent=pcie-controller@10003000
pci_uclass_post_probe: probing bus 1
pci_bind_bus_devices: bus 1/pci_0:1.0: found device 0, function 0
pci_find_and_bind_driver: Searching for driver: vendor=10ee, device=9024
pci_find_and_bind_driver: No match found: bound generic driver instead
pci_auto_config_devices: start
pci_auto_config_devices: device pci_1:0.0
pci_auto_config_devices: done
pci_get_bus_max: ret=1
pci_auto_config_devices: done
4 !!! uclass_next_device
4 !!! uclass_next_device
Tegra186 (P2771-0000-500) #

5

We are not clear on what is the question here?

  1. Is there a way to find out which BAR address was assigned to a PCIe device?
    Ans: I guess the debug prints need to be added to get this info??
  2. Is there a way to access memory in a PCIe device’s BAR?
    Ans: Yes; the md command should work fine for this just like regular DRAM. I don’t * think * that a probed U-Boot driver is required for the BAR region to be enabled in the MMU.
  3. Something else?
7

There is no update from you for a period, assuming this is not an issue any more.
Hence we are closing this topic. If need further support, please open a new one.
Thanks

Hi jack.hsia,

Is this stull an issue to support? Any result can be shared?