Why I2C_GP5 mapping to /dev/i2c-8

I use the Jetson AGX Xavier+carrier board B02, and it connect the I2C device (Addr=0x56) via 40-pin expansion header on carrier board.

CPU: Jetson AGX Xavier (32GB)(P2888-0004)
Carrier board: Jetson AGX Xavier Carrier board (180-82822-DAAF-B02)

I check the schematic of carrier board B02, and see the pin3 and pin5 of 40-pin expansion header are I2C_GP5_DAT and I2C_GP5_CLK, and it connect to the I2C_GP5_DAT and I2C5_CLK of CVM of Xavier module.

But I can’t use i2c-5 to read I2C device 0x56, and it get fail.
I need to use i2c-8 to read I2C deivice 0x56.

root@nvidia-xavier:~# i2cget -y 8 0x2B 0x00 w

Why I2C_GP5_DAT and I2C_GP5_CLK is i2c-8?

Check this for reference.

I still can’t understand why I2C_GP5 is /dev/ic2-8? not /dev/i2c-5?
Does it any mapping information in datasheet?

Have a check the pinmux xlsm file. The I2C1_XX SFIO is the I2C9_xx, I2C9 is map to software count 8

I see the SFIO1=I2C9 in pin mux.
Thank you very much.