Why some pins should have GPIO function but not marked in TX2 pinmux document?

Hi JerryChang,

What the difference between “Pinmux and GPIOs configuration” and “Prod setting” in https://docs.nvidia.com/jetson/archives/l4t-archived/l4t-322/index.html#page/Tegra%2520Linux%2520Driver%2520Package%2520Development%2520Guide%2Fmb1_platform_config_tx2.html%23wwpID0E0QK0HA?

Pin 8 in J21 of tx2, the relative net lable is UART1_TXD_HDR_3V3, which this UART1_TX name belongs to, signal name or IC ball name?

I don’t know how to configure those pins. It seem we can make it through dtsi file or pinmux file. Please do us a favor.

hello garretzou,

As documentation described,
MB1 only allows writes to the pinmux and GPIO address range. prod setting is the configuration of system characterization, interface, and controller settings.
you may also refer to Jetson TX2 Boot Flow for the flow of control in MB1.

Such these settings in the device tree (dtsi file) are still applied by the kernel.
hope this helps,

Thank you so much.

Please take a look at the question in fifth floor.

We want UART3_TX(IC ball name) as GPIO, can we and how to?

Is the pin 8 in J21 the UART3_TX(IC ball name) in pinmux document 1.00?

External Image

UART3_TX(IC ball name) in pinmux document
External Image

UART3_TX register
External Image

External Image

Provided UART3_TX corresponds to pin8 in J21. I tried to configure it as GPIO following below steps,
(1) change tegra186-mb1-bct-pinmux-quill-p3310-1000-c03.cfg file

pinmux.0x0c302020 = 0x00000011; # uart3_tx_pw2: gpio, tristate-enable, input-disable, lpdr-disable

(2) generate new image l4t(32.2.1)

sudo ./flash --no-flash jetson-tx2 external

(3) flash the system.img to internal eMMC

./flash -r jetson-tx2 mmcblk0p1

PS.: The rootfs is copied to a external SD card.
(4) write value to GPIO282 in /sys/class/gpio

echo 282 > /sys/class/gpio/export
echo out > /sys/class/gpio/gpio282/direction
echo 0 > /sys/class/gpio/gpio282/value

But the voltage of pin8 is always 3.3v.

Hi Garretzou,

I am adding some more data to JerryChang’s reply for your reference.

Yes most but not all of the pins on 40-pin header can be configured as GPIO.
And some of them are preset to SFIO based on user requirements and some pins are forced configured as SFIO.

This is tricky. Because the pinmux spreadsheet is prepared based on user requirements, so the GPIO selection is not provided for few of them. If you want to know the particular GPIO bank and port, here is a quick hack.
Check in the pinmux cfg source. (say $TEGRA_TOP/bct/t186/pinmux/tegra186-mb1-bct-pinmux-quill-p3310-1000-c03.cfg)
Say you are trying to configure CAN1_DOUT pin as GPIO.
Now look for “can1_dout” under the section #### Pinmux for used pins ####
The entry is:
pinmux.0x0c303008 = 0x00000400; # can1_dout_pz0: can1, tristate-disable, input-disable
can1_dout_pz0 this tells that GPIO configuration is (Z, 0)

Both xxx_pinmux_xxx.dtsi and tegra186-mb1-bct-pinmux-quill-p3310-1000-c03.cfg can configure pin function. What the relation between them?

Pinmux is configured during MB1 which is early boot phase. For MB1, the configuration tables are supplied with *.cfg. Our earlier SoCs which has dtsi settings configured in kernel, use dtsi version.

Please let us know if you have any more concerns.

Thanks & Regards,

Hi JerryChang,
Thank you so much.

That means one pin configured as GPIO in pinmux BCT file while as SFIO in dtsi file will finally be GPIO. But the BCT file is loaded prior to the dtsi. That makes me confused.

Hi, Sandipan,

Thanks for your kindly reply. Great help for us.

Please take a look at the 8th floor questions?

Hi garretzou,

I am also seeing same thing on my setup.
We are looking at it. Will revert back to you in sometime.

Thanks & Regards,

In the Jetson-TX2-Series-Pinmux-Template.xlsm Revision 1.00 there is the PEX_CLK pins A44, A45, A41, A42, B45, B46. These are all listed under the first sections before you get to the “Dedicated SFIOs” section on row 249. Similarly, under the EDP section there are pins B35, B34, A35, and A34. Cells AQ234 and AQ235 make it look like they can be configured between I2C6_CLK/DAT and DP_AUX_CH0_P/N. However, I can’t find the proper pinmux register for any of these pins.

Are any of these pins pinmux configurable?

Can they be configured as GPIOs?

If not, why are they not listed in the “Dedicated SFIOs” section?

Many thanks.

Please just give me a hints an tips about how to configure UART3_TX(IC ball name) as GPIO if it can be? Our intense work schedule is obstructed by this GPIO issue greatly.

Hi garretzou,

We are looking at this.
Can you please let us know how are you configuring the pin as gpio?

Hi spatra,


Please refer the fifth and eighth floor.

Hi garretzou,

Following pins on 40 pin header, they are going to level shifter which restricts their direction.

So the pins whose DIR is OUT, voltage can be Low/High in OUT state of GPIO, cannot drive the pin in IN state.
Same goes with Pins in IN DIR. Direction of these pins cannot be changed as they are hardware restricted.

Shubhi Garg

I think you have the signal connection path incorrect. From your earlier post #8, it looks like you are trying to control the J21 expansion header pin 8. Correct?

Here is the hardware path from the Jetson TX2 SoM to that pin:
Jetson TX2 H12 pin → UART0_TXD → UART MUX (U8) → UART0_TXD_HDR_1V8 → Level Shifter (U5) → UART1_TXD_HDR_3V3 → J21 pin 8

So if you want to control J21 pin 8, you need to configure the GPIO for pin H12 on the SoM. This maps to the IC Ball Name UART1_TX and is controlled by PADCTL_DEBUG_UART1_TX_0 @0x02435018. This corresponds with GPIO Port T.00 (GPIO #464).

Therefore, all you need to do is set GPIO #464 properly to the value you would like in order to control J21 pin 8. For example:

root@nvtegra:~# devmem2 0x02435018
Read at address  0x02435018 (0x7fa035d018): 0x00000400
root@nvtegra:~# echo 464 > /sys/class/gpio/export 
root@nvtegra:~# echo out > /sys/class/gpio/gpio464/direction 
root@nvtegra:~# devmem2 0x02435018
Read at address  0x02435018 (0x7f89f8f018): 0x00000000
root@nvtegra:~# echo 1 > /sys/class/gpio/gpio464/value #set J21 pin 8 HIGH
root@nvtegra:~# echo 0 > /sys/class/gpio/gpio464/value #set J21 pin 8 LOW
root@nvtegra:~# echo 1 > /sys/class/gpio/gpio464/value #set J21 pin 8 HIGH
root@nvtegra:~# echo 0 > /sys/class/gpio/gpio464/value #set J21 pin 8 LOW

The only way UART1_TXD_HDR_3V3 maps to UART3_TXD (still not Tegra UART3) is if you have populated a jumper for R79 and removed the jumper at R80 on your development kit.

I’ve went ahead and updated the existing spreadsheet to include all of the GPIOs properly listed. See the attached unofficial v1.01 of the spreadsheet.
[This file was removed because it was flagged as potentially malicious] (1.1 MB)

Dear JDSchroeder,
Thanks a lot.

We will have a try.

Dear JDSchroeder,

The Jetson-TX2i-TX2-4GB-Template wasn’t updated in Jetson-TX2-Series-Pinmux-Template-v101.zip. Could you also update it? Our product uses TX2-4GB module.

Dear JerryChang,

Thanks for your explanation.
I am still not clear about the difference between pinmux_config(tegra186-mb1-bct-pinmux-quill-p3310-1000-c03.cfg) and bootloader_dtb(tegra186-quill-p3310-1000-c03-00-base.dtb). I know some pin can configure by either pinmux_config or bootloader_dtb, which file finally make sense?

I generate a tegra18x-jetson-tx2-config-template-gpio-default.dtsi file, but how could I make this dtsi configuration work? I have tried many method, but seem not work.

Hi JDSchroeder,

Please help us update the pinmux document of tx2-4G.

hello garretzou,

you’ll need to check Jetson TX2 Boot Flow for reference,
in short, bootloader (MB1) load the cfg file for firmware initialization.
dtb file were loaded while kernel initialize, it’ll also overwrite several configurations.