Hello DRAMESH
Thank you.I pass the fixed mclk clock to FPGA-CODEC driver.There are some questions which i want to ask for help.
1.In my board,There are two codecs.one is rt5640 acting as slave base on IIS1,the other one is FPGA-CODEC acting as master base on IIS2.when i play file wav through rt5640,I find the plla/pll_out/mclk will update because of the different sample rate,such as 48K,44.1K or 16K.but when i arecord through my FPGA-CODEC which act as master, the pll/pll_out/mclk also update depending on the sample rate,is this normal? in fact,in this situation,the mclk is driven by FPGA_CODEC. if driver could’t update pll/pll_out/mclk,is this OK?
2.Does the codecs possess the same clock tree about plla/pll_out/mclk?There are two codecs in my board base on IIS1 and IIS2.I play wav file through IIS1 base on different sample rate,the pll/pll_out/mclk will update.but when i play wav file through IIS2 base in different sample rate,the same pll/pll_out/mclk will update too.if so there is a problem in the following situation.I play wav file 48K through IIS1,and at the same time I play wav file 16K through IIS2.There must are murmur because of plla/pll_out/mclk are not match for both 16k and 48K?Does this mean two codecs can’t work normal at the same time?
Thank you