Brief System Description
JetPack 4.6.2 L4T 32.7.2
NVidia Jetson AGX Xavier Module 32GB - Non Industrial Version
Marvell 88Q5072 11 Port Switch
The Marvell switch is connected to the Xavier via RGMII interface. So this is a MAC to MAC connection.
To bring the switch to a operational level we need to configure some Marvell switch registers via the MDIO interface.
Requirements:
- Support a MAC to MAC connection
- Support MDIO access to configure the Marvell switch.
Our question is about the correct device tree entries to accomplish these 2 requirements.
The device tree we begin with follows:
ether_qos@2490000 {
compatible = "nvidia,eqos";
...
OMITED PROPERTIES FOR BREVITY
...
phy-mode = "rgmii-id";
phy-handle = <0x1f>;
vddio_sys_enet_bias-supply = <0x20>;
vddio_enet-supply = <0x20>;
phy_vdd_1v8-supply = <0x21>;
phy_ovdd_rgmii-supply = <0x21>;
phy_pllvdd-supply = <0x20>;
mdio {
compatible = "nvidia,eqos-mdio";
#address-cells = <0x01>;
#size-cells = <0x00>;
ethernet-phy@0 {
reg = <0x00>;
phy_rst_lp_mode = <0x01>;
interrupt-parent = <0x12>;
interrupts = <0x34 0x08>;
marvell,copper-mode;
marvell,reg-init = <0x03 0x12 0x7fff 0x880>;
linux,phandle = <0x1f>;
phandle = <0x1f>;
};
};
};
For the MAC to MAC connection we need to add the following:
fixed-link {
speed = <100>;/* Mbs */
full-duplex;
};
We came up with the following however phytool could no longer read / write the MDIO bus.
ether_qos@2490000 {
compatible = "nvidia,eqos";
...
OMITED PROPERTIES FOR BREVITY
...
phy-mode = "rgmii-id";
//phy-handle = <0x1f>;
vddio_sys_enet_bias-supply = <0x20>;
vddio_enet-supply = <0x20>;
phy_vdd_1v8-supply = <0x21>;
phy_ovdd_rgmii-supply = <0x21>;
phy_pllvdd-supply = <0x20>;
mdio {
compatible = "nvidia,eqos-mdio";
#address-cells = <0x01>;
#size-cells = <0x00>;
};
fixed-link {
speed = <100>;/* Mbs */
full-duplex;
};
};
We would like some help determining the correct device tree configuration to support our requirements?