A few questions about PCIe apertures in TRM document

Hey everyone,
I’m here to ask a few questions that may seem dumb. I was reading Xavier Series SoC Technical Reference Manual, and saw that there are two different type of PCIe apertures in AMAP. One of those is for 32-bit OSes, while the other is for 64. However, when I checked https://developer.nvidia.com/EMBEDDED/linux-tegra%20, the toolchain (gcc and such) supplied from NVIDIA is specified as for 64-bit BSP and Kernel. So my questions here are:

I) Is it possible to compile a 32-bit kernel with the supplied tools and sources?
II) If not, then why does the document somehow suggest that we can?
III) If possible, PCIe aperture is shown as 256 MB in AMAP overview table, but also mentioned as 32 MB per PCIe controller, which is 32*6=192 MB sections below the table. If this place even can be used ( I is posssible), how to correctly use this space?
IV) Is using a 32-bit OS on NX okay, what would a developer lose if s/he don’t use 64-bits (other than a larger PCIe aperture)?

Thanks for your time.

There is no 32bits kernel support for AGX Xavier and Xavier NX.
For TRM, that’s HW spec, please refer to below docs for SW development:

And L4T R32.4.2 Feature List

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OK, my bad. Thanks for the reference, I’ll dig into it ASAP.