About Jetson AGX Orin SDIO interface voltage issue

Autonomous Machines Jetson & Embedded Systems Jetson AGX Orin
1

Hi teachers，
Orin’s SDIO interface is connected to an eMMC，when we tested the signal, we found that the signal amplitude of D0~D3 is greater than 1.8V, which is about 2.2V, what is the reason?
See below for a schematic. Thanks.

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image1920×1382 172 KB

3

Hi, only SD CARD or SDIO is supported as you can see in Design Gudie.

4

Yea, I only connected a emmc ,and my sdio voltage is 1.8V, but the measured voltage is about 2.2V as you seen in the third figure. And I want to know what caused ?

6

Please add “only-1-8-v” to your device tree node.

Basically, just copy the sdmmc4 node as that one is on board emmc.

7

Hi Wayne，
My eMMC configuration is shown below，please check it for me，thank you.

sdmmc1: sdhci@3400000 {
compatible = “nvidia,tegra234-sdhci”, “nvidia,tegra194-sdhci”;
reg = <0x0 0x3400000 0x0 0x00020000>;
interrupts = < 0 TEGRA234_IRQ_SDMMC1 0x04>;
#if TEGRA_IOMMU_DT_VERSION >= DT_VERSION_2
interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA>,
<&mc TEGRA234_MEMORY_CLIENT_SDMMCWA>;
interconnect-names = “dma-mem”, “dma-mem”;
#endif
iommus = <&smmu_niso1 TEGRA_SID_NISO1_SDMMC1A>;
dma-coherent;
max-clk-limit = <200000000>;
ddr-clk-limit = <51000000>;
bus-width = <4>;
only-1-8-v;
ignore-pm-notify;
keep-power-in-suspend;
non-removable;
cap-mmc-highspeed;
cap-sd-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
#if TEGRA_SDMMC_VERSION >= DT_VERSION_2
nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
nvidia,pad-autocal-pull-down-offset-1v8-timeout =
<0x0a>;
nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
nvidia,pad-autocal-pull-down-offset-3v3-timeout =
<0x0a>;
nvidia,default-tap = <18>;
nvidia,default-trim = <0x7>;
nvidia,dqs-trim = <40>;
assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>;
assigned-clock-parents =
<&bpmp TEGRA234_CLK_PLLC4_MUXED>;

#endif
resets = <&bpmp_resets TEGRA234_RESET_SDMMC1>;
reset-names = “sdhci”;
pll_source = “pll_p”, “pll_c4_muxed”;
nvidia,set-parent-clk;
nvidia,parent_clk_list = “pll_p”, “pll_p”, “pll_p”, “pll_p”, “pll_p”, “pll_c4_muxed”, “pll_c4_muxed”, “pll_c4_muxed”, “pll_c4_muxed”, “pll_c4_muxed”, “NULL”;
clocks = <&bpmp_clks TEGRA234_CLK_SDMMC1>,
<&bpmp_clks TEGRA234_CLK_PLLP_OUT0>,
<&bpmp_clks TEGRA234_CLK_PLLC4_MUXED>,
<&bpmp_clks TEGRA234_CLK_SDMMC_LEGACY_TM>,
<&bpmp_clks TEGRA234_CLK_SDMMC_LEGACY_TM>;
clock-names = “sdmmc”, “pll_p”, “pll_c4_muxed”, “sdmmc_legacy_tm”, “tmclk”;
status = “disabled”;
};

9

There is no update from you for a period, assuming this is not an issue any more.
Hence we are closing this topic. If need further support, please open a new one.
Thanks

Sorry for the late response, is this still an issue to support? Thanks