After i2cset test, nano can't boot in eMMC boot evironment

Autonomous Machines Jetson & Embedded Systems Jetson Nano
6

Hi,

It has been a while so I need to recap this issue.

  1. Are you able to flash the board after all the patches we shared to you?

  2. Where does this UART log come from? Right after your flash?

7

Thank you for your response.

Are you able to flash the board after all the patches we shared to you?

Yes. I can flash board, but it couldn’t launch U-Boot.

Where does this UART log come from? Right after your flash?

Yes. right after execute following command.

$ sudo ./flash.sh jetson-nano-emmc mmcblk0p1

Could you give me some clear recovery instruction from extracting L4T archive.
Thanks.

8

Hi,

Need some more detail about this.

Do you hit this error after applying our patch or even before applying the patch?

Yes. right after execute following command.
$ sudo ./flash.sh jetson-nano-emmc mmcblk0p1

Could you also share your flash log with us?

9

Hi,

I also notice you guys may put the nvtboot binary to rel-32.3.1 environment. But the binary is actually for earlier release. So please

1.Try other method except the nvtboot binary if you are using rel-32.3.1.
2. Try to downgrade to rel-32.1 and run with nvtboot binary and see if it can flash and boot up.

10

Do you hit this error after applying our patch or even before applying the patch?

Even before applying the patch.

First of all, we found this(after i2cset test, nano can't boot - #95 by lonesomesnow) thread and write nvtboot.bin/nvtboot_recovery.bin
that #40(after i2cset test, nano can't boot - #40 by WayneWWW) attached.

$ strings nvtboot.bin | grep 2018
00.00.2018.01-l4t-a2563f57

and then we could see UART output, but it happend another error like “Error in NvTbootLoadBinary: 0x1 !”.

Could you also share your flash log with us?

I attached it.
20200701_00_UART.log (9.8 KB)
20200701_00_FLASHLOG.log (14.3 KB)

11

Hi,

I guess you miss my previous comment so let me put it here again.

I also notice you guys may put the nvtboot binary to rel-32.3.1 environment. But the binary is actually for earlier release. So please
1.Try other method except the nvtboot binary if you are using rel-32.3.1.
2. Try to downgrade to rel-32.1 and run with nvtboot binary and see if it can flash and boot up.

In brief, that nvtboot binary may only work for rel-32.1 so I don’t suggest your to use that. Please try other methods first. I guess that one which adds the xml file should resolve the flash problem.

Or you could just go back to rel-32.1 and see if this can make it work.

12

Hi,

Or you could just go back to rel-32.1 and see if this can make it work.

I did it like after i2cset test, nano can't boot - #51 by lonesomesnow

Our boot device is eMMC, so we used jetson-nano-qspi.conf.

Step 1: uncompress Jetson-Nano-Tegra210_Linux_R32.1.0_aarch64.tbz2
Step 2: uncompress Jetson-Nano-Tegra_Linux_Sample-Root-Filesystem_R32.1.0_aarch64.tbz2
Step 3: run “sudo ./apply_binaries.sh”
Step 4: uncompress nvtboot_20190711.tar.gz downloaded and put

nvtboot.bin to Linux_for_Tegra/bootloader/t210ref,
nvtboot_recovery.bin to Linux_for_Tegra/bootloader,

Step 5: modify jetson-nano-qspi.conf

[Linux_for_Tegra/p3448-0000.conf]

BOARDID="3448";
FAB="4";
BOARDSKU="0002" ;
BOARDREV="70";
EMMC_CFG=flash_l4t_t210_spi_p3448.xml;
source "${LDK_DIR}/p3448-0000.conf.common";

Step 6: set Nano to RCM

Step 7: use command “sudo ./flash.sh jetson-nano-qspi mmcblk0p1” to flash

And yielded the “EEPROM CRC failed” error.

UART

[0087.218] Enabled early print
[0087.221] [TegraBoot] (version 00.00.2018.01-l4t-175e178b)
[0087.226] Processing in recovery mode
[0087.229] A02 Bootrom Patch rev = 1023
[0087.233] Power-up reason: pmc por
[0087.236] NvTbootClockInit()
[0087.239] Established communication link with host
[0088.219] Module[6] Instance[0]Updating CLK_RST_CTRL Register [0x360] with 0x80400808
[0088.228] Odmdata from BCT: 0x00094000
[0088.231] DebugPort= 0x3
[0088.234] Reading board info Type: 1
[0088.237] Module[1] Instance[0]Updating CLK_RST_CTRL Register [0x4] with 0x1c93d288
[0088.244] Module[1] Instance[0]Updating CLK_RST_CTRL Register [0x124] with 0xc0000000
[0088.252] Module[1] Instance[0]Using Clock Divisor: 0x0[0088.257] Module[1] Instance[0]Updating CLK_RST_CTRL Register [0x124] with 0xc0000000
[0088.265] Module[1] Instance[0]Updating CLK_RST_CTRL Register [0x10] with 0x80401170
[0088.273] Module[1] Instance[0]Updating CLK_RST_CTRL Register [0x4] with 0x1c93c288
[0088.301] Module[1] Instance[2]Updating CLK_RST_CTRL Register [0xc] with 0x828ec5fa
[0088.309] Module[1] Instance[2]Updating CLK_RST_CTRL Register [0x1b8] with 0xc0000000
[0088.316] Module[1] Instance[2]Using Clock Divisor: 0x0[0088.321] Module[1] Instance[2]Updating CLK_RST_CTRL Register [0x1b8] with 0xc0000000
[0088.329] Module[1] Instance[2]Updating CLK_RST_CTRL Register [0x18] with 0x1f00208
[0088.337] Module[1] Instance[2]Updating CLK_RST_CTRL Register [0xc] with 0x828ec5f2
[0088.372] EEPROM CRC failed. Calculated crc=0xe3 CRC stored = 0xb6
[0088.378] WARNING: Eeprom verification failed, Error = 20
[0088.383] Board Type: 1, Board Id: 0
[0088.386] Reading Board-ID for Board-Type-1 unsuccessful
[0088.391] BoardId read from EEPROM/NCT: 0
[0088.395] Unsupported Platform 0
[0088.398] Downloaded BCT successfully

20200701_rel321_UART.log (1.8 KB)
20200701_rel321_FLASHLOG.log (245.8 KB)

13

Hi,

Not sure if you notice or not. The real solution that resolved this issue on rel-32.1 is in below patch.

Maybe there is no need to use the nvtboot at all but just this step. Please try.

14

Hi,

Not sure if you notice or not. The real solution that resolved this issue on rel-32.1 is in below patch.

I fixed files like following.

[p3448-0000.conf.common]

...
EKSFILE="bootloader/eks.img";
BCT="--bct ";
VERFILENAME="qspi_bootblob_ver.txt";
BCFFILE="bootloader/${target_board}/cfg/board_config_p3448.xml";
NULL_INITRD_IN_BOOTIMG="yes";


[bootloader/t210ref/cfg/board_config_p3448.xml]
<?xml version="1.0"?>

<!-- Nvidia Tegra board info configuration file -->

<board_configs>
    <board type="proc" id="3448" sku="0000" fab="0" />
    <board type="display" id="0xffff" sku="0000"/>
    <board type="pmu" id="3448" sku="0000" />
</board_configs>

And yielded the Error loading Bootloader DTB" error.

UART

[0134.887] Enabled early print
[0134.890] [TegraBoot] (version 00.00.2018.01-l4t-175e178b)
[0134.895] Processing in recovery mode
[0134.898] A02 Bootrom Patch rev = 1023
[0134.902] Power-up reason: pmc por
[0134.905] NvTbootClockInit()
[0134.908] Established communication link with host
[0135.887] Module[6] Instance[0]Updating CLK_RST_CTRL Register [0x360] with 0x80400808
[0135.895] Odmdata from BCT: 0x00094000
[0135.899] DebugPort= 0x3
[0135.901] Reading board info Type: 1
[0135.905] Board Type: 1, Board Id: 3448
[0135.908] BoardId read from EEPROM/NCT: 3448
[0135.913] NvTbootInit_Porg: entry …
[0135.916] Board Info for Type: 1 already read
[0135.920] Board Type: 1, Board Id: 3448
[0135.924] BoardID = 3448, SKU = 0x0
[0135.927] NvTbootInit_Porg: calling Max77620Setup …
[0135.932] Module[1] Instance[4]Updating CLK_RST_CTRL Register [0x8] with 0x8000
[0135.939] Module[1] Instance[4]Updating CLK_RST_CTRL Register [0x128] with 0xc0000000
[0135.947] Module[1] Instance[4]Using Clock Divisor: 0x0[0135.952] Module[1] Instance[4]Updating CLK_RST_CTRL Register [0x128] with 0xc0000000
[0135.959] Module[1] Instance[4]Updating CLK_RST_CTRL Register [0x14] with 0x20080c1
[0135.968] Module[1] Instance[4]Updating CLK_RST_CTRL Register [0x8] with 0x0
[0135.975] Module[11] Instance[0]Updating CLK_RST_CTRL Register [0x35c] with 0x190037ff
[0135.983] Module[11] Instance[0]Updating CLK_RST_CTRL Register [0x364] with 0x482000fc
[0135.992] Module[11] Instance[0]Updating CLK_RST_CTRL Register [0x35c] with 0x110037ff
[0136.021] NvTbootInit_Porg: calling PorgRecovery …
[0136.025] NvTbootInit_Porg: calling Fastboot w/platformops …
[0136.031] NvTboot_Fastboot: PMC_SCRATCH0 Fastboot flag = 0
[0136.036] NvTbootInit_Porg: returning, code = 0 …
[0136.041] UART-A
[0136.043] No Battery Present
[0136.045] RamCode = 0
[0136.048] Board Info for Type: 1 already read
[0136.052] Board Type: 1, Board Id: 3448
[0136.056] Platform has DDR4 type RAM
[0136.059] max77620 disabling SD1 Remote Sense
[0136.063] Setting DDR voltage to 1125mv
[0136.067] Serial Number of Pmic Max77663: 0xd15ee
[0136.072] Volt Vsel Val = 0x2a
[0136.075] NvTbootEnableMemClock()
[0136.078] NvTbootInitPllM()[0136.080] NvTbootClocksStartPll()
[0136.083] NvTbootClocksIsPllStable()
[0136.087] NvTbootAssertMemReset()[0136.092] Entering ramdump check
[0136.095] Get RamDumpCarveOut = 0x0
[0136.099] RamDumpCarveOut=0x0, RamDumperFlag=0xe59ff3f8
[0136.104] Last reboot was clean, booting normally!
[0136.108] Sdram initialization is successful
[0136.113] SecureOs Carveout Base=0x00000000ff800000 Size=0x00800000
[0136.119] Lp0 Carveout Base=0x00000000ff780000 Size=0x00001000
[0136.125] BpmpFw Carveout Base=0x00000000ff700000 Size=0x00080000
[0136.131] GSC1 Carveout Base=0x00000000ff600000 Size=0x00100000
[0136.136] GSC2 Carveout Base=0x00000000ff500000 Size=0x00100000
[0136.142] GSC4 Carveout Base=0x00000000ff400000 Size=0x00100000
[0136.148] GSC5 Carveout Base=0x00000000ff300000 Size=0x00100000
[0136.154] GSC3 Carveout Base=0x000000017f300000 Size=0x00d00000
[0136.170] RamDump Carveout Base=0x00000000ff280000 Size=0x00080000
[0136.176] Platform-DebugCarveout: 0
[0136.180] Downloaded BCT successfully
[0136.305] Downloaded Bootloader successfully
[0136.352] Downloaded rp1 successfully
[0136.376] Board Info for Type: 1 already read
[0136.380] Board Type: 1, Board Id: 3448
[0136.384] MAX77620_GPIO5 configured
[0136.388] CPU power rail is up
[0136.391] NvTbootEnableCpuClock()
[0136.394] CPU clock enabled
[0136.396] Module[10] Instance[0]Updating CLK_RST_CTRL Register [0x1d4] with 0x0
[0136.403] Module[10] Instance[0]Using Clock Divisor: 0x4[0136.408] Module[10] Instance[0]Updating CLK_RST_CTRL Register [0x1d4] with 0x4
[0136.415] Module[10] Instance[0]Updating CLK_RST_CTRL Register [0x18] with 0x1f00200
[0136.424] Performing RAM repair
[0136.427] Updating A64 Warmreset Address to 0x92c002e9
[0136.433] Enable APE clock/reset
[0136.436] Module[16] Instance[0]Updating CLK_RST_CTRL Register [0x6c0] with 0x80000000
[0136.444] Module[16] Instance[0]Using Clock Divisor: 0x2[0136.449] Module[16] Instance[0]Updating CLK_RST_CTRL Register [0x6c0] with 0x80000002
[0136.457] Module[16] Instance[0]Updating CLK_RST_CTRL Register [0x298] with 0x340
[0136.464] Module[16] Instance[0]Updating CLK_RST_CTRL Register [0x2a4] with 0xfe9f09d
[0136.472] Error in NvTbootGetTOSBinaryLength: 0x11 !
[0136.477] Loading Secure OS image failed.
[0136.480] Set NvDecSticky Bits
[0136.483] Module[13] Instance[0]Updating CLK_RST_CTRL Register [0x180] with 0x80000000
[0136.491] Module[13] Instance[0]Using Clock Divisor: 0x3[0136.496] Module[13] Instance[0]Updating CLK_RST_CTRL Register [0x180] with 0x80000003
[0136.504] Module[13] Instance[0]Updating CLK_RST_CTRL Register [0x10] with 0x90400171
[0136.511] Module[13] Instance[0]Updating CLK_RST_CTRL Register [0x4] with 0xc93d288
[0136.519] Module[14] Instance[0]Updating CLK_RST_CTRL Register [0x698] with 0x80000000
[0136.527] Module[14] Instance[0]Using Clock Divisor: 0x0[0136.532] Module[14] Instance[0]Updating CLK_RST_CTRL Register [0x698] with 0x80000000
[0136.539] Module[14] Instance[0]Updating CLK_RST_CTRL Register [0x298] with 0x344
[0136.547] Module[14] Instance[0]Updating CLK_RST_CTRL Register [0x2a4] with 0xfe9f099
[0136.554] Module[15] Instance[0]Updating CLK_RST_CTRL Register [0x69c] with 0x80000000
[0136.562] Module[15] Instance[0]Using Clock Divisor: 0x0[0136.567] Module[15] Instance[0]Updating CLK_RST_CTRL Register [0x69c] with 0x80000000
[0136.575] Module[15] Instance[0]Updating CLK_RST_CTRL Register [0x298] with 0x34c
[0136.582] Module[15] Instance[0]Updating CLK_RST_CTRL Register [0x2a4] with 0xfe9f091
[0136.590] Module[15] Instance[0]Updating CLK_RST_CTRL Register [0x2a4] with 0xfe9f099
[0136.597] Module[15] Instance[0]Updating CLK_RST_CTRL Register [0x298] with 0x344
[0136.605] Module[14] Instance[0]Updating CLK_RST_CTRL Register [0x2a4] with 0xfe9f09d
[0136.612] Module[14] Instance[0]Updating CLK_RST_CTRL Register [0x298] with 0x340
[0136.620] Module[13] Instance[0]Updating CLK_RST_CTRL Register [0x4] with 0x1c93d288
[0136.627] Module[13] Instance[0]Updating CLK_RST_CTRL Register [0x10] with 0x80400171
[0136.635] setting GSC1 MC params
[0136.639] setting GSC2 MC params
[0136.642] GSC2 address ff53fffc value c0edbbcc
[0136.647] setting GSC3 MC params
[0136.650] setting GSC4 MC params
[0136.654] setting GSC5 MC params
[0136.657] GSC MC Settings done
[0136.661] Next binary entry address: 0x92c00258
[0136.666] BoardId: 3448
[0136.668] Board Info for Type: 1 already read
[0136.672] Reading board info Type: 2
[0136.676] Board Info for Type: 1 already read
[0136.680] Board Type: 1, Board Id: 3448
[0136.684] Reading board info Type: 3
[0136.687] revision 1
[0136.689] crc 0x1bb0aa39
[0136.692] early uart 0x70006000
[0136.695] dram bottom 0xfefff000
[0136.698] boot dev=0 instance=3
[0136.701] storage dev=2 instance=0
[0136.705] uid is 0x100581c0 0x4000000 0x64456807 0x1
[0136.710] carveout[0] base:0x00000000 size: 0x00000000
[0136.715] carveout[1] base:0x80000000 size: 0x7efff000
[0136.720] carveout[2] base:0x80000000 size: 0x00000000
[0136.725] carveout[3] base:0x00000000 size: 0x00000000
[0136.730] carveout[4] base:0x00000000 size: 0x00000000
[0136.735] carveout[5] base:0xff800000 size: 0x00800000
[0136.740] carveout[6] base:0xff780000 size: 0x00001000
[0136.745] carveout[7] base:0x00000000 size: 0x00000000
[0136.750] carveout[8] base:0x00000000 size: 0x00000000
[0136.755] carveout[9] base:0xff700000 size: 0x00080000
[0136.760] carveout[10] base:0xff280000 size: 0x00080000
[0136.765] carveout[11] base:0xff600000 size: 0x00100000
[0136.770] carveout[12] base:0xff500000 size: 0x00100000
[0136.775] carveout[13] base:0x7f300000 size: 0x00d00000
[0136.780] carveout[14] base:0xff400000 size: 0x00100000
[0136.786] carveout[15] base:0xff300000 size: 0x00100000
[0136.791] carveout[16] base:0x00000000 size: 0x00000000
[0136.796] carveout[17] base:0x00000000 size: 0x00000000
[0136.801] carveout[18] base:0x00000000 size: 0x7f300000
[0136.806] bct size is 10240
[0136.809] tboot offset is 262144
[0136.812] dram memory type is 3
[0136.815] block size 32768
[0136.817] page size 2048
[0136.820] boot type 2
[0136.822] Opmode 3
[0136.824] powerkey long press 0
[0136.827] rollback version 2
[0136.830] rollback enable yes
[0136.833] rollback level-boot 0
[0136.836] rollback level-tos 0
[0136.839] rollback level-tsec 1
[0136.842] rollback level-nvdec 1
[0136.845] EKS valid state no
[0136.848] Printing reserved section
[0136.851] 0 [0136.852] 0 [0136.853] 0 [0136.855] 0 [0136.856] 0 [0136.857] 0 [0136.858] 0 [0136.859] 0 [0136.860] 0 [0136.862] 0 [0136.863] 0 [0136.864] 0 [0136.865] 0 [0136.866] 0 [0136.867] 0 [0136.869] 0 [0136.870] 0 [0136.871] 0 [0136.872] 0 [0136.873] 0 [0136.874] 0 [0136.876] 0 [0136.877] 0 [0136.878] 0 [0136.879] 0 [0136.880] 0 [0136.882] 0 [0136.883] 0 [0136.884] 0 [0136.885] 0 [0136.886] 0 [0136.887] 0 [0136.889] 0 [0136.890] 0 [0136.891] 0 [0136.892] 0 [0136.893] 0 [0136.894] 0 [0136.896] 0 [0136.897] 0 [0136.898] 0 [0136.899] 0 [0136.900] 0 [0136.901] 0 [0136.903] 0 [0136.904] 0 [0136.905] 0 [0136.906] 0 [0136.907] 0 [0136.908] 0 [0136.910] 0 [0136.911] 0 [0136.912] 0 [0136.913] 0 [0136.914] 0 [0136.915] 0 [0136.917] 0 [0136.918] 0 [0136.919] 0 [0136.920] 0 [0136.921] 0 [0136.922] 0 [0136.924] 0 [0136.925] 0 [0136.926] 0 [0136.927] 0 [0136.928] 0 [0136.930] 0 [0136.931] 0 [0136.932] 0 [0136.933] 0 [0136.934] 0 [0136.935] 0 [0136.937] 0 [0136.938] 0 [0136.939] 0 [0136.940] 0 [0136.941] 0 [0136.942] 0 [0136.944] 0 [0136.945] 0 [0136.946] 0 [0136.947] 0 [0136.948] 0 [0136.949] 0 [0136.951] 0 [0136.952] 0 [0136.953] 0 [0136.954] 0 [0136.955] 0 [0136.956] 0 [0136.958] 0 [0136.959] 0 [0136.960] 0 [0136.961] 0 [0136.962] 0 [0136.963] 0 [0136.965] 0 [0136.966] 0 [0136.967] 0 [0136.968] 0 [0136.969] 0 [0136.970] 0 [0136.972] 0 [0136.973] 0 [0136.974] 0 [0136.975] 0 [0136.976] 0 [0136.978] 0 [0136.979] 0 [0136.980] 0 [0136.981] 0 [0136.982] 0 [0136.983] 0 [0136.985] 0 [0136.986] 0 [0136.987] 0 [0136.988] 0 [0136.989] 0 [0136.990] 0 [0136.992] 0 [0136.993] 0 [0136.994] 0 [0136.995] 0 [0136.996] 0 [0136.997] 0 [0136.999] 0 [0137.000] 0 [0137.001] 0 [0137.002] 0 [0137.003] 0 [0137.004] 0 [0137.006] 0 [0137.007] 0 [0137.008] 0 [0137.009] 0 [0137.010] 0 [0137.011] 0 [0137.013] 0 [0137.014] 0 [0137.015] 0 [0137.016] 0 [0137.017] 0 [0137.019] 0 [0137.020] 0 [0137.021] 0 [0137.022] 0 [0137.023] 0 [0137.024] 0 [0137.026] 0 [0137.027] 0 [0137.028] 0 [0137.029] 0 [0137.030] 0 [0137.031] 0 [0137.033] 0 [0137.034] 0 [0137.035] 0 [0137.036] 0 [0137.037] 0 [0137.038] 0 [0137.040] 0 [0137.041] 0 [0137.042] 0 [0137.043] 0 [0137.044] 0 [0137.045] 0 [0137.047] 0 [0137.048] 0 [0137.049] 0 [0137.050] 0 [0137.051] 0 [0137.052] 0 [0137.054] 0 [0137.055] 0 [0137.056] 0 [0137.057] 0 [0137.058] 0 [0137.059] 0 [0137.061] 0 [0137.062] 0 [0137.063] 0 [0137.064] 0 [0137.065] 0 [0137.067] 0 [0137.068] 0 [0137.069] 0 [0137.070] 0 [0137.071] 0 [0137.072] 0 [0137.074] 0 [0137.075] 0 [0137.076] 0 [0137.077] 0 [0137.078] 0 [0137.079] 0 [0137.081] 0 [0137.082] 0 [0137.083] 0 [0137.084] 0 [0137.085] 0 [0137.086] 0 [0137.088] 0 [0137.089] 0 [0137.090] 0 [0137.091] 0 [0137.092] 0 [0137.093] 0 [0137.095] 0 [0137.096] 0 [0137.097] 0 [0137.098] 0 [0137.099] 0 [0137.100] 0 [0137.102] 0 [0137.103] 0 [0137.104] 0 [0137.105] 0 [0137.106] 0 [0137.107] 0 [0137.109] 0 [0137.110] 0 [0137.111] 0 [0137.112] 0 [0137.113] 0 [0137.115] 0 [0137.116] 0 [0137.117] 0 [0137.118] 0 [0137.119] 0 [0137.120] 0 [0137.122] 0 [0137.123] 0 [0137.124] Board Info for Type: 1 already read
[0137.128] Board Type: 1, Board Id: 3448
[0137.132] Starting CPU & Halting co-processor

[0137.136] NvTbootAssertCpuReset()
[0137.139] Halting AVP
[0140.437]
[0140.438] Debug Init done
[0140.441] -9: Bad DTB Header. dtb_type = 0
[0140.445] panic (caller 0x92c02008): Error loading Bootloader DTB
[0140.451] HALT: spinning forever…

20200701_2_rel321_UART.log (11.8 KB)
20200701_2_rel321_FLASHLOG.log (243.9 KB)

15

Is your carrier board the A02 one or the B01 one?

17

If it is emmc, then you could only use some new release like rel-32.2 or rel-32.3.

In such case, please just put the xml file and patch in conf to there and try again.

Please just forget about the nvtboot. Do not use it on rel-32.3 anymore.

18

To be more precisely, I think the only solution that was once resolved the issue on rel-32.1 is

This solution should work on rel-32.3.1 as well.
The other solutions like nvtboot was not working at all. Please just forget about them.

If even this patch does not work, then it is totally a new issue. We need to check log.

19

Hi,

This solution should work on rel-32.3.1 as well.

I did it in rel-32.3.1 like following step.

Step 1: uncompress Tegra210_Linux_R32.3.1_aarch64.tbz2

Step 2: uncompress Tegra_Linux_Sample-Root-Filesystem_R32.3.1_aarch64.tbz2

Step 3: run “sudo ./apply_binaries.sh”

Step 4: modify p3448-0000.conf.common

[Linux_for_Tegra/p3448-0000.conf.common]
…
BCT="–bct ";
VERFILENAME=“qspi_bootblob_ver.txt”;
BCFFILE=“bootloader/${target_board}/cfg/board_config_p3448.xml”;

Step 5: confirm board_config_p3448.xml

file content was already same as after i2cset test, nano can't boot - #89 by WayneWWW

 <?xml version="1.0"?>

 <!-- Nvidia Tegra board info configuration file -->

 <board_configs>
     <board type="proc" id="3448" sku="0000" fab="0" />
     <board type="display" id="0xffff" sku="0000"/>
     <board type="pmu" id="3448" sku="0000" />
 </board_configs>

Step 6: set Nano to RCM

Step 7: use command “sudo ./flash.sh jetson-nano-emmc mmcblk0p1” to flash

And yielded the “Parsing board information failed”.

Do we need any additional fix?
Thanks.

UART

[0004.138] Enabled early print
[0004.141] [L4T TegraBoot] (version 00.00.2018.01-l4t-1463e5a5)
[0004.147] Processing in recovery mode
[0004.150] A02 Bootrom Patch rev = 1023
[0004.153] Power-up reason: pmc por
[0004.157] Established communication link with host
[0005.158] NvTbootI2cWrite(): error code 0x00045100 Error while starting write transaction
[0005.166] NvTbootI2cDeviceRead(): error code 0x00045001 Error while sending the offset to slave
[0005.174] NvTbootI2c: Read failed for slave 0xac, offset 0x00 with error code 0x00045001

FLASHLOG

shin@shin-miniPC:~/work/tmp2/Linux_for_Tegra$ sudo ./flash.sh jetson-nano-emmc mmcblk0p1
###############################################################################
# L4T BSP Information:
# R32 , REVISION: 3.1
###############################################################################
# Target Board Information:
# Name: jetson-nano-emmc, Board Family: t210ref, SoC: Tegra 210, 
# OpMode: production, Boot Authentication: , 
###############################################################################
./tegraflash.py --chip 0x21 --applet "/home/shin/work/tmp2/Linux_for_Tegra/bootloader/nvtboot_recovery.bin" --skipuid --cmd "dump eeprom boardinfo cvm.bin" 
Welcome to Tegra Flash
version 1.0.0
Type ? or help for help and q or quit to exit
Use ! to execute system commands
 
[   0.0011 ] Generating RCM messages
[   0.0021 ] tegrarcm --listrcm rcm_list.xml --chip 0x21 0 --download rcm /home/shin/work/tmp2/Linux_for_Tegra/bootloader/nvtboot_recovery.bin 0 0
[   0.0030 ] RCM 0 is saved as rcm_0.rcm
[   0.0036 ] RCM 1 is saved as rcm_1.rcm
[   0.0036 ] List of rcm files are saved in rcm_list.xml
[   0.0036 ] 
[   0.0036 ] Signing RCM messages
[   0.0045 ] tegrasign --key None --list rcm_list.xml --pubkeyhash pub_key.key
[   0.0054 ] Assuming zero filled SBK key
[   0.0106 ] 
[   0.0107 ] Copying signature to RCM mesages
[   0.0117 ] tegrarcm --chip 0x21 0 --updatesig rcm_list_signed.xml
[   0.0131 ] 
[   0.0132 ] Boot Rom communication
[   0.0142 ] tegrarcm --chip 0x21 0 --rcm rcm_list_signed.xml --skipuid
[   0.0152 ] RCM version 0X210001
[   0.0565 ] Boot Rom communication completed
[   1.0631 ] 
[   1.0632 ] dump EEPROM info
[   1.0657 ] tegrarcm --oem platformdetails eeprom /home/shin/work/tmp2/Linux_for_Tegra/bootloader/cvm.bin
[   1.0678 ] Applet version 00.01.0000
[   1.0859 ] Saved platform info in /home/shin/work/tmp2/Linux_for_Tegra/bootloader/cvm.bin
[   1.1625 ] 
Parsing board information failed.
20

Could you change your sku number from 0000 to 0002? and fab to 400?

 <board type="proc" id="3448" sku="0000" fab="0" />

Please compare the uart log and see if anything change.
If it does not, please move to rel-32.4.2.

21

Hi,

Could you change your sku number from 0000 to 0002? and fab to 400?

[bootloader/t210ref/cfg/boar_config_p3448.xml]

<?xml version="1.0"?>

<!-- Nvidia Tegra board info configuration file -->

<board_configs>
    <board type="proc" id="3448" sku="0002" fab="400" />
    <board type="display" id="0xffff" sku="0000"/>
    <board type="pmu" id="3448" sku="0000" />
</board_configs>

And yielded the same result like “Parsing board information failed”.

Refer to following comment in flash.sh,

# BOARDID ---------------- Pass boardid to override EEPROM value
# BOARDREV --------------- Pass board_revision to override EEPROM value
# BOARDSKU --------------- Pass board_sku to override EEPROM value
# BOOTLOADER ------------- Bootloader binary to be flashed

I added to VARS like this.

[p3448-0000-emmc.conf]

BOARDID=“3448”;
FAB=“400”;
BOARDSKU=“0002” ;
BOARDREV=“70”;

Then, we passed “Parsing board information failed”,
but stopped at “Flushing data to stroage”.

[0008.921] Found 17 GPT partitions in “sdmmc3_user”
[0008.925] Proceeding to flashing Server
[0008.929] usbdcd_reinit Initialize driver to use already enumerated device
[0008.936] nv3p_priv_usbf_open USB configuration success
[0008.944] Writing LNX partition
[0008.997] partition LNX write successful.
[0009.011] Writing BCT partition
[0009.403] partition BCT write successful.
[0009.417] Change state to cold boot mode
[0009.421] Flushing data to stroage

Is that helpful to you?
If we want to override EEPROM value, Shouldn’t we have to define it as a variable in *.conf?

20200702_rel32.3.1_sku_fab_UART.txt (5.9 KB)
20200702_rel32.3.1_sku_fab_FLASHLOG.txt (15.0 KB)

1 Like
22

If we want to override EEPROM value, Shouldn’t we have to define it as a variable in *.conf?

There is no way to override eeprom value on host.

Could you also try rel-32.4.2?

23

Hey… why your log shows you are flashing -k LNX ? You should use the full flash command.

shin@shin-miniPC:~/work/tmp2/Linux_for_Tegra$ sudo ./flash.sh -k LNX jetson-nano-emmc mmcblk0p1

24

Hi,

Hey… why your log shows you are flashing -k LNX ? You should use the full flash command.

Sorry for about that. I mistakenly add -k LNX temporarily.
But I used to run " sudo ./flash.sh jetson-nano-emmc mmcblk0p1" all the time.

And “Overriding board information” seems work for me.

Sort out the situation, I did the following steps.

Step 1: uncompress Tegra210_Linux_R32.3.1_aarch64.tbz2

Step 2: uncompress Tegra_Linux_Sample-Root-Filesystem_R32.3.1_aarch64.tbz2

Step 3: run “sudo ./apply_binaries.sh”

Step 4: add BCFFILE to [p3448-0000.conf.common]

[Linux_for_Tegra/p3448-0000.conf.common]
…
BCT="–bct ";
VERFILENAME=“qspi_bootblob_ver.txt”;
+BCFFILE=“bootloader/${target_board}/cfg/board_config_p3448.xml”;

Step 5: add some BOARDINFO to [p3448-0000-emmc.conf]

[Linux_for_Tegra/p3448-0000-emmc.conf]
…
+BOARDID=“3448”;
+FAB=“400”;
+BOARDSKU=“0002” ;
+BOARDREV=“70”;

EMMC_CFG=flash_l4t_t210_emmc_p3448.xml;
BLBlockSize=1048576;
source “${LDK_DIR}/p3448-0000.conf.common”;
T21BINARGS="–bins "EBT cboot.bin; "
CMDLINE_ADD=“console=ttyS0,115200n8 console=tty0 fbcon=map:0 net.ifnames=0 sdhci_tegra.en_boot_part_access=1”;

ROOTFSSIZE=14GiB;
VERFILENAME=“emmc_bootblob_ver.txt”;

Step 6: set Nano to RCM

Step 7: use command “sudo ./flash.sh jetson-nano-emmc mmcblk0p1” to flash

Then , entire flash succeeded and confirmed that start up Linux Kernel.

20200703_rel32.3.1_override_UART.txt (27.7 KB)
20200703_rel32.3.1_override_FLASHLOG.txt (22.9 KB)

From the conclusion, in my environment,
・No need to use nvtboot_20190711.tar.gz.
・Need to define BCFFILE.
・Need to override BOARDINFO in Step 5.

There is no way to override eeprom value on host.

Not sure if you notice or not, the source of override BOARDINFO is after i2cset test, nano can't boot - #35 by WayneWWW.

In my understanding,
the board information in EEPROM cannot use due to CRC error,
I think it is necessary to override on the host side.

Thank you for your support.

Regards.

1 Like
25

Yes, after system boots up, please use i2cset to modify eeprom to correct checksum value.

26