Greetings Nvidia Family,
We plan to design custom carrier board for Tx2/Tx2i.
We need 3x USB 3.0 (independent 5Gb/sec x 3) + 1 USB 2.0 (OTG) and Sata.
As we know correctly, Tx2/Tx2i can give us 3x USB 3.0 (Config 4) but they use same USB controller and that’s why bandwidth will split to 3.
Based on Table 16 and Figure 15 in Jetson Tx2/Tx2i OEM Product Design Guide and Refer to this topic:
[url]https://devtalk.nvidia.com/default/topic/1027100/jetson-tx2/stream-4-cameras-with-gstreamer/post/5225245/#5225245[/url]
We can use PCIe 1x4 slot to get 2 more USB 3.0 (5Gb/s x 2). But this PCIe cards use PCIe switches.
We have very limited space that why we don’t want to use PCIe Switch.
To achive this we need Config 5 right?
Our pin out idea:
Can we implement PCIe lanes with this method to get 3x USB 3.0 (5GB/sec x 3 ) [Connector 2,3,4] and Sata at the same time independently?
And if we need 4x USB 3.0 (5GB/sec x 4 ) we need to sacrifice SATA right? (case of SATA_DEV_SLP and PEX1_CLKREQ# have same mux controller)
Thank you.
Hi,
Please refer to TRM:
USB 3.0 Ports
USB 3.0 ports only operate in USB 3.0 Super Speed mode. USB 3.0 port 0 is allocated with one Super Speed unit bandwidth,
while USB 3.0 port 1 and port 2 share another Super Speed Bus Instance. This means USB 3.0 port 0 can fully utilize 5 Gb/s
theoretical bandwidth, and another 5 Gb/s theoretical bandwidth is distributed between USB 3.0 port 1 and port 2.
Which means for 3x USB3.0, if you use PCIe converter for USB3.0, then config #3, #4, #5, #6 can meet that.
SATA on TX2 is gen2, 3.0Gbps, can’t meet the request.
Please consider your design with the constraint.
Hi DaneL,
Thank you for your feedback.
Please correct me if i am wrong.
For config#4 theoretically we can get 4x USB 3.0 [5Gb/s for every port], USB 2.0 OTG and Sata [3Gb/s] at the same time.
And can you verify my pin mapping for 3x USB3.0 lanes?
PCIe#0_0 (PCIe to USB bridge)
A44 / A45…PEX0_REFCLK+/-
C48…PEX0_CLKREQ#
C49…PEX0_RST#
E44 / E45…PEX0_TX+/-
H44 / H45…PEX0_RX+/-
D48…PEX_WAKE#
PCIe#1_0 (PCIe to USB bridge)
A41 / A42…PEX2_REFCLK+/-
C46…PEX2_CLKREQ#
D49…PEX2_RST#
C40 / C41…PEX2_TX+/-
F40 / F41…PEX2_RX+/-
D48…PEX_WAKE#
USB_SS#2 (USB 3.0)
B42/B43…USB2_D+/-
A19…USB2_EN_OC#
D42/D43…USB_SS1_TX+/-
G42/G43…USB_SS1_RX+/-
Thank you for your help.
Hi Danel,
Sorry for my late replay.
Thank you for confirmation my pin mapping.
I will remove A19 from design.
Thank you for your help.
