I’m trying to debug a set of SErrors in the kernel log - such as:
[ 3641.615008] CPU0: SError detected, daif=1c0, spsr=0x200000c5, mpidr=80000100, esr=bf000002
[ 3641.615010] CPU3: SError detected, daif=1c0, spsr=0x800000c5, mpidr=80000101, esr=bf40c000
[ 3641.615012] CPU5: SError detected, daif=1c0, spsr=0x200000c5, mpidr=80000103, esr=bf40c000
[ 3641.615032] CPU2: SError detected, daif=1c0, spsr=0x800000c5, mpidr=80000001, esr=be000000
[ 3641.615039] CPU1: SError detected, daif=140, spsr=0x20000000, mpidr=80000000, esr=be000000
[ 3641.615113] CPU4: SError detected, daif=140, spsr=0x20000000, mpidr=80000102, esr=bf40c000
[ 3641.615141] CPU0: SError detected, daif=1c0, spsr=0x200000c5, mpidr=80000100, esr=bf40c000
I’m currently mainly trying to figure out what the esr register values mean. I’ve found a description in the ARM Architecture Reference Manual, but from what I can see, all the register values from the A57 cores have the “Implementation Defined” bit set (bit [25]), and the ARM manual doesn’t provide any further information on that.
I’ve had a look through the TX2/Parker TRM also, but can’t find anything related to the contents of that register.
Anyone who can point me in the correct direction?