Hello,
This is a follow on to the solution I got working in this previous thread: Jetson Nano DisplayPort Force - Bypass EDID
The problem I am seeing is that this solution works very well once it is up and running it is stable once it is up with HBR2/4 lanes. However it only comes up ~1/10 times the DP sink is plugged. What I see happening is that on the hot plug event the DP display is showing up in the System Settings control panel with the correct resolution, however the whole UI becomes very laggy and unresponsive until I unplug the display and then it reverts to normal. About 1/10 times it does not show this problem and the UI works fine, DP display works fine, etc. I have verified that this does not follow any particular display or cable. I have tried multiple DP sinks and multiple DP cables and the issue is the same so I do not believe it is an SI issue or an issue with the panel itself.
Looking deeper on the issue in the kernel logs, I can see when this happens that the DP link training is not completing for some reason. In fact, the link training doesn’t even get past the CR stage. Again, in the normal case, the link training completes successfully and the sink trains to the full HBR2 rate with 4 lanes at the lowest VOD settings so it seems that the SI quality is good.
Here is the log of what is happening in the failing case. Can you help me diagnose specifically what is happening here and how to fix it? I’m thinking it has something to do with the timing of the AUX transactions in relation to the hot plug event since the EDID bypass is enabled so the link training should be theoretically starting earlier than normal? It is strange to me that 1/10 times it actually trains without any issue and can work error free.
[ 158.728561] hpd: Display connected, hpd_switch 1
[ 158.728565] hpd: switching from state 2 (Check EDID) to state 4 (Enabled)
[ 158.761437] dp lt: state 5 (link training pass), pending_lt_evt 1
[ 158.761441] dp lt: switching from state 5 (link training pass) to state 0 (Reset)
[ 158.761444] dp lt: state 0 (Reset), pending_lt_evt 0
[ 158.761449] dp lt: link training force disable
[ 158.761451] dp lt: switching from state 0 (Reset) to state 4 (link training fail/disable)
[ 158.837578] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[ 158.837610] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10000080 did not specify bpp
[ 158.837636] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10000000 did not specify bpp
[ 158.837660] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10000080 did not specify bpp
[ 158.837684] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10000000 did not specify bpp
[ 158.837707] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10000080 did not specify bpp
[ 158.837730] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10000080 did not specify bpp
[ 158.837754] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10000080 did not specify bpp
[ 158.837780] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10000000 did not specify bpp
[ 158.837804] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10000080 did not specify bpp
[ 158.837827] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10000080 did not specify bpp
[ 158.837850] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10000000 did not specify bpp
[ 158.837876] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10000000 did not specify bpp
[ 158.837899] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10000080 did not specify bpp
[ 158.837922] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10000080 did not specify bpp
[ 158.837946] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10000080 did not specify bpp
[ 158.837971] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10000000 did not specify bpp
[ 158.837995] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10000080 did not specify bpp
[ 158.838019] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10000080 did not specify bpp
[ 158.838043] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10000000 did not specify bpp
[ 158.838067] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10000000 did not specify bpp
[ 158.838091] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10000080 did not specify bpp
[ 158.838116] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10000080 did not specify bpp
[ 158.838139] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10000000 did not specify bpp
[ 158.840914] tegradc tegradc.0: unblank
[ 158.840926] tegradc tegradc.1: blank - powerdown
[ 158.955104] tegradc tegradc.0: unblank
[ 158.955117] tegradc tegradc.1: blank - powerdown
[ 159.005250] tegradc tegradc.0: unblank
[ 159.005269] tegradc tegradc.1: blank - powerdown
[ 159.005290] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[ 159.005307] tegradc tegradc.1: unblank
[ 159.039990] tegradc tegradc.1: nominal-pclk:148500000 parent:148500000 div:1.0 pclk:148500000 147015000~161865000
[ 159.042033] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[ 159.045659] tegradc tegradc.1: DP: no prod_c_hbr2 prod settings node in device tree
[ 159.050240] dp lt: state 4 (link training fail/disable), pending_lt_evt 1
[ 159.050243] dp lt: switching from state 4 (link training fail/disable) to state 0 (Reset)
[ 159.050245] dp lt: state 0 (Reset), pending_lt_evt 0
[ 159.051398] tegradc tegradc.1: DP: no prod_c_hbr2 prod settings node in device tree
[ 159.051559] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
[ 159.051565] dp lt: state 2 (clock recovery), pending_lt_evt 0
[ 159.051811] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[ 159.051824] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[ 159.051838] dp lt: config: lane 2: vs level: 0, pe level: 0, pc2 level: 0
[ 159.051851] dp lt: config: lane 3: vs level: 0, pe level: 0, pc2 level: 0
[ 159.051858] dp lt: tx_pu: 0x20
[ 159.053208] dp lt: CR not done
[ 159.053883] dp lt: new config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[ 159.053885] dp lt: new config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[ 159.053888] dp lt: new config: lane 2: vs level: 1, pe level: 0, pc2 level: 0
[ 159.053890] dp lt: new config: lane 3: vs level: 1, pe level: 0, pc2 level: 0
[ 159.053892] dp lt: CR retry
[ 159.053895] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
[ 159.053899] dp lt: state 2 (clock recovery), pending_lt_evt 0
[ 159.053915] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[ 159.053928] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[ 159.053941] dp lt: config: lane 2: vs level: 1, pe level: 0, pc2 level: 0
[ 159.053954] dp lt: config: lane 3: vs level: 1, pe level: 0, pc2 level: 0
[ 159.053960] dp lt: tx_pu: 0x30
[ 159.055312] dp lt: CR not done
[ 159.055982] dp lt: new config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[ 159.055984] dp lt: new config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[ 159.055986] dp lt: new config: lane 2: vs level: 2, pe level: 0, pc2 level: 0
[ 159.055988] dp lt: new config: lane 3: vs level: 2, pe level: 0, pc2 level: 0
[ 159.055989] dp lt: CR retry
[ 159.055992] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
[ 159.055995] dp lt: state 2 (clock recovery), pending_lt_evt 0
[ 159.056011] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[ 159.056025] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[ 159.056038] dp lt: config: lane 2: vs level: 2, pe level: 0, pc2 level: 0
[ 159.056051] dp lt: config: lane 3: vs level: 2, pe level: 0, pc2 level: 0
[ 159.056056] dp lt: tx_pu: 0x40
[ 159.057404] dp lt: CR not done
[ 159.058078] dp lt: new config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[ 159.058081] dp lt: new config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[ 159.058083] dp lt: new config: lane 2: vs level: 3, pe level: 0, pc2 level: 0
[ 159.058085] dp lt: new config: lane 3: vs level: 3, pe level: 0, pc2 level: 0
[ 159.058086] dp lt: CR retry
[ 159.058089] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
[ 159.058093] dp lt: state 2 (clock recovery), pending_lt_evt 0
[ 159.058110] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[ 159.058123] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[ 159.058137] dp lt: config: lane 2: vs level: 3, pe level: 0, pc2 level: 0
[ 159.058151] dp lt: config: lane 3: vs level: 3, pe level: 0, pc2 level: 0
[ 159.058156] dp lt: tx_pu: 0x60
[ 159.059507] dp lt: CR not done
[ 159.060174] dp lt: new config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[ 159.060176] dp lt: new config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[ 159.060177] dp lt: new config: lane 2: vs level: 3, pe level: 0, pc2 level: 0
[ 159.060179] dp lt: new config: lane 3: vs level: 3, pe level: 0, pc2 level: 0
[ 159.060180] dp lt: CR retry
[ 159.060183] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
[ 159.060186] dp lt: state 2 (clock recovery), pending_lt_evt 0
[ 159.060202] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[ 159.060214] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[ 159.060227] dp lt: config: lane 2: vs level: 3, pe level: 0, pc2 level: 0
[ 159.060240] dp lt: config: lane 3: vs level: 3, pe level: 0, pc2 level: 0
[ 159.060245] dp lt: tx_pu: 0x60
[ 159.061603] dp lt: CR not done
[ 159.062276] dp lt: new config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[ 159.062279] dp lt: new config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[ 159.062281] dp lt: new config: lane 2: vs level: 3, pe level: 0, pc2 level: 0
[ 159.062283] dp lt: new config: lane 3: vs level: 3, pe level: 0, pc2 level: 0
[ 159.062285] dp lt: CR retry
[ 159.062287] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
[ 159.062291] dp lt: state 2 (clock recovery), pending_lt_evt 0
[ 159.062307] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[ 159.062321] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[ 159.062335] dp lt: config: lane 2: vs level: 3, pe level: 0, pc2 level: 0
[ 159.062348] dp lt: config: lane 3: vs level: 3, pe level: 0, pc2 level: 0
[ 159.062354] dp lt: tx_pu: 0x60
[ 159.063702] dp lt: CR not done
[ 159.064369] dp lt: new config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[ 159.064371] dp lt: new config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[ 159.064374] dp lt: new config: lane 2: vs level: 3, pe level: 0, pc2 level: 0
[ 159.064376] dp lt: new config: lane 3: vs level: 3, pe level: 0, pc2 level: 0
[ 159.064377] dp lt: CR retry
[ 159.064381] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
[ 159.064385] dp lt: state 2 (clock recovery), pending_lt_evt 0
[ 159.064402] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[ 159.064416] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[ 159.064430] dp lt: config: lane 2: vs level: 3, pe level: 0, pc2 level: 0
[ 159.064444] dp lt: config: lane 3: vs level: 3, pe level: 0, pc2 level: 0
[ 159.064450] dp lt: tx_pu: 0x60
[ 159.065799] dp lt: CR not done
[ 159.066472] dp lt: new config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[ 159.066475] dp lt: new config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[ 159.066477] dp lt: new config: lane 2: vs level: 3, pe level: 0, pc2 level: 0
[ 159.066479] dp lt: new config: lane 3: vs level: 3, pe level: 0, pc2 level: 0
[ 159.066481] dp lt: CR adj retry limit 5 reached
[ 159.066484] dp lt: switching from state 2 (clock recovery) to state 6 (reduce link rate)
[ 159.066488] dp lt: state 6 (reduce link rate), pending_lt_evt 0
[ 159.067925] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
[ 159.067953] dp lt: retry CR, lanes: 4, link rate: 0xa
[ 159.067956] dp lt: switching from state 6 (reduce link rate) to state 2 (clock recovery)
[ 159.067961] dp lt: state 2 (clock recovery), pending_lt_evt 0
[ 159.068216] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[ 159.068230] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[ 159.068243] dp lt: config: lane 2: vs level: 0, pe level: 0, pc2 level: 0
[ 159.068256] dp lt: config: lane 3: vs level: 0, pe level: 0, pc2 level: 0
[ 159.068262] dp lt: tx_pu: 0x20
[ 159.069635] dp lt: CR not done
[ 159.070316] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
[ 159.070318] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
[ 159.070321] dp lt: new config: lane 2: vs level: 1, pe level: 0, pc2 level: 0
[ 159.070323] dp lt: new config: lane 3: vs level: 1, pe level: 0, pc2 level: 0
[ 159.070325] dp lt: CR retry
[ 159.070328] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
[ 159.070333] dp lt: state 2 (clock recovery), pending_lt_evt 0
[ 159.070350] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
[ 159.070363] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
[ 159.070376] dp lt: config: lane 2: vs level: 1, pe level: 0, pc2 level: 0
[ 159.070389] dp lt: config: lane 3: vs level: 1, pe level: 0, pc2 level: 0
[ 159.070395] dp lt: tx_pu: 0x30
[ 159.071759] dp lt: CR not done
[ 159.072434] dp lt: new config: lane 0: vs level: 2, pe level: 0, pc2 level: 0
[ 159.072436] dp lt: new config: lane 1: vs level: 2, pe level: 0, pc2 level: 0
[ 159.072438] dp lt: new config: lane 2: vs level: 2, pe level: 0, pc2 level: 0
[ 159.072441] dp lt: new config: lane 3: vs level: 2, pe level: 0, pc2 level: 0
[ 159.072442] dp lt: CR retry
[ 159.072445] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
[ 159.072449] dp lt: state 2 (clock recovery), pending_lt_evt 0
[ 159.072465] dp lt: config: lane 0: vs level: 2, pe level: 0, pc2 level: 0
[ 159.072478] dp lt: config: lane 1: vs level: 2, pe level: 0, pc2 level: 0
[ 159.072491] dp lt: config: lane 2: vs level: 2, pe level: 0, pc2 level: 0
[ 159.072505] dp lt: config: lane 3: vs level: 2, pe level: 0, pc2 level: 0
[ 159.072510] dp lt: tx_pu: 0x40
[ 159.073875] dp lt: CR not done
[ 159.074555] dp lt: new config: lane 0: vs level: 3, pe level: 0, pc2 level: 0
[ 159.074558] dp lt: new config: lane 1: vs level: 3, pe level: 0, pc2 level: 0
[ 159.074560] dp lt: new config: lane 2: vs level: 3, pe level: 0, pc2 level: 0
[ 159.074562] dp lt: new config: lane 3: vs level: 3, pe level: 0, pc2 level: 0
[ 159.074564] dp lt: CR retry
[ 159.074566] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
[ 159.074570] dp lt: state 2 (clock recovery), pending_lt_evt 0
[ 159.074586] dp lt: config: lane 0: vs level: 3, pe level: 0, pc2 level: 0
[ 159.074599] dp lt: config: lane 1: vs level: 3, pe level: 0, pc2 level: 0
[ 159.074612] dp lt: config: lane 2: vs level: 3, pe level: 0, pc2 level: 0
[ 159.074626] dp lt: config: lane 3: vs level: 3, pe level: 0, pc2 level: 0
[ 159.074631] dp lt: tx_pu: 0x60
[ 159.076032] dp lt: CR not done
[ 159.076712] dp lt: new config: lane 0: vs level: 3, pe level: 0, pc2 level: 0
[ 159.076715] dp lt: new config: lane 1: vs level: 3, pe level: 0, pc2 level: 0
[ 159.076717] dp lt: new config: lane 2: vs level: 3, pe level: 0, pc2 level: 0
[ 159.076720] dp lt: new config: lane 3: vs level: 3, pe level: 0, pc2 level: 0
[ 159.076721] dp lt: max vs reached
[ 159.076724] dp lt: switching from state 2 (clock recovery) to state 6 (reduce link rate)
[ 159.076729] dp lt: state 6 (reduce link rate), pending_lt_evt 0
[ 159.078162] tegradc tegradc.1: DP: no prod_c_rbr prod settings node in device tree
[ 159.078191] dp lt: retry CR, lanes: 4, link rate: 0x6
[ 159.078194] dp lt: switching from state 6 (reduce link rate) to state 2 (clock recovery)
[ 159.078198] dp lt: state 2 (clock recovery), pending_lt_evt 0
[ 159.078442] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[ 159.078455] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[ 159.078469] dp lt: config: lane 2: vs level: 0, pe level: 0, pc2 level: 0
[ 159.078482] dp lt: config: lane 3: vs level: 0, pe level: 0, pc2 level: 0
[ 159.078488] dp lt: tx_pu: 0x20
[ 159.079859] dp lt: CR not done
[ 159.080543] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
[ 159.080546] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
[ 159.080548] dp lt: new config: lane 2: vs level: 1, pe level: 0, pc2 level: 0
[ 159.080551] dp lt: new config: lane 3: vs level: 1, pe level: 0, pc2 level: 0
[ 159.080552] dp lt: CR retry
[ 159.080555] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
[ 159.080560] dp lt: state 2 (clock recovery), pending_lt_evt 0
[ 159.080578] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
[ 159.080592] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
[ 159.080606] dp lt: config: lane 2: vs level: 1, pe level: 0, pc2 level: 0
[ 159.080620] dp lt: config: lane 3: vs level: 1, pe level: 0, pc2 level: 0
[ 159.080626] dp lt: tx_pu: 0x30
[ 159.082001] dp lt: CR not done
[ 159.082688] dp lt: new config: lane 0: vs level: 2, pe level: 0, pc2 level: 0
[ 159.082690] dp lt: new config: lane 1: vs level: 2, pe level: 0, pc2 level: 0
[ 159.082693] dp lt: new config: lane 2: vs level: 2, pe level: 0, pc2 level: 0
[ 159.082695] dp lt: new config: lane 3: vs level: 2, pe level: 0, pc2 level: 0
[ 159.082697] dp lt: CR retry
[ 159.082700] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
[ 159.082704] dp lt: state 2 (clock recovery), pending_lt_evt 0
[ 159.082722] dp lt: config: lane 0: vs level: 2, pe level: 0, pc2 level: 0
[ 159.082736] dp lt: config: lane 1: vs level: 2, pe level: 0, pc2 level: 0
[ 159.082751] dp lt: config: lane 2: vs level: 2, pe level: 0, pc2 level: 0
[ 159.082765] dp lt: config: lane 3: vs level: 2, pe level: 0, pc2 level: 0
[ 159.082771] dp lt: tx_pu: 0x40
[ 159.084415] dp lt: CR not done
[ 159.085149] dp lt: new config: lane 0: vs level: 3, pe level: 0, pc2 level: 0
[ 159.085151] dp lt: new config: lane 1: vs level: 3, pe level: 0, pc2 level: 0
[ 159.085154] dp lt: new config: lane 2: vs level: 3, pe level: 0, pc2 level: 0
[ 159.085156] dp lt: new config: lane 3: vs level: 3, pe level: 0, pc2 level: 0
[ 159.085157] dp lt: CR retry
[ 159.085161] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
[ 159.085165] dp lt: state 2 (clock recovery), pending_lt_evt 0
[ 159.085183] dp lt: config: lane 0: vs level: 3, pe level: 0, pc2 level: 0
[ 159.085196] dp lt: config: lane 1: vs level: 3, pe level: 0, pc2 level: 0
[ 159.085208] dp lt: config: lane 2: vs level: 3, pe level: 0, pc2 level: 0
[ 159.085220] dp lt: config: lane 3: vs level: 3, pe level: 0, pc2 level: 0
[ 159.085225] dp lt: tx_pu: 0x60
[ 159.086590] dp lt: CR not done
[ 159.087280] dp lt: new config: lane 0: vs level: 3, pe level: 0, pc2 level: 0
[ 159.087282] dp lt: new config: lane 1: vs level: 3, pe level: 0, pc2 level: 0
[ 159.087285] dp lt: new config: lane 2: vs level: 3, pe level: 0, pc2 level: 0
[ 159.087287] dp lt: new config: lane 3: vs level: 3, pe level: 0, pc2 level: 0
[ 159.087289] dp lt: max vs reached
[ 159.088724] tegradc tegradc.1: DP: no prod_c_rbr prod settings node in device tree
[ 159.088755] dp lt: switching from state 2 (clock recovery) to state 4 (link training fail/disable)
[ 159.088770] dp lt: state 4 (link training fail/disable), pending_lt_evt 0
[ 159.088773] dp lt: NULL state handler in state 4
[ 159.105915] tegradc tegradc.1: unblank