DSI display: does tegra_dsi_read_data() work?

Hi,

What we want to achieve is prior to sending the init-cmd, read the display IDs (0xDA 0xDB 0xDC)
To that end we are using tegra_dsi_read_data()
The display works fine in video mode after init-cmd is sent on this tx2 platform

Reading panel registers on TX2 results in FIFO being empty and a 218ms timeout with nvhost_syncpt_wait_timeout_ext()

the display responds superfast (~400ns) after IMM_BTA is given, we measured this with logical analyzer on the mipi lane. However this response ends with a timeout and empty fifo. here you can see the full 0x37 request and 0x06 read, and display answer followed by 218ms timeout in dsi.c:nvhost_syncpt_wait_timeout_ext().

zoomed in on request packets

zoomed in on display response:

We have a different platform with AM335x+toshiba mipi that reads the display fine and response can be read (so the display response is normal):

back on the TX2: added some logging to the kernel to see if we can understand what is going on.

echo "0x01 0xDA" >/sys/kernel/debug/tegra_dsi/read_panel
cat /sys/kernel/debug/tegra_dsi/read_panel
[    2.449366] tegradc 15200000.nvdisplay: tegra_dsi_set_to_lp_mode 4
[    2.449369] tegradc 15200000.nvdisplay: tegra_dsi_set_to_lp_mode 5
[    2.457873] tegradc 15200000.nvdisplay: tegra_dsi_set_to_lp_mode 6
[    2.457887] tegradc 15200000.nvdisplay: tegra_dsi_set_to_lp_mode 7
[    2.457890] tegradc 15200000.nvdisplay: tegra_dsi_set_control_reg_lp
[    2.457897] tegradc 15200000.nvdisplay: tegra_dsi_set_to_lp_mode 8
[    2.457908] tegradc 15200000.nvdisplay: tegra_dsi_set_to_lp_mode 9
[    2.473122] tegradc 15200000.nvdisplay: tegra_dc_dsi_display_detect select dsi_init_cmd
[    2.474906] tegradc 15200000.nvdisplay: tegra_dsi_read_data_cmd pad_control_cd: 0
[    2.474910] tegradc 15200000.nvdisplay: tegra_dsi_read_data_cmd pad_control_cd written: 30000
[    2.474931] tegradc 15200000.nvdisplay: tegra_dsi_syncpt 7e dsi->syncpt_val+1:1 syncpt_id:b syncpt:0
[    2.474938] tegradc 15200000.nvdisplay: tegra_dsi_read_data_cmd max_threshold 1
[    2.474943] tegradc 15200000.nvdisplay: tegra_dsi_set_to_lp_mode 4
[    2.474945] tegradc 15200000.nvdisplay: tegra_dsi_set_to_lp_mode 5
[    2.483485] tegradc 15200000.nvdisplay: tegra_dsi_set_to_lp_mode 6
[    2.483500] tegradc 15200000.nvdisplay: tegra_dsi_set_to_lp_mode 7
[    2.483503] tegradc 15200000.nvdisplay: tegra_dsi_set_control_reg_lp
[    2.483510] tegradc 15200000.nvdisplay: tegra_dsi_set_to_lp_mode 8
[    2.483512] tegradc 15200000.nvdisplay: tegra_dsi_set_to_lp_mode 9
[    2.483515] tegradc 15200000.nvdisplay: tegra_dsi_bta 1 !!!!!!
[    2.483519] tegradc 15200000.nvdisplay: tegra_dsi_bta 2
218ms
[    2.702022] tegradc 15200000.nvdisplay: tegra_dsi_syncpt 7e dsi->syncpt_val+1:2 syncpt_id:b syncpt:0
[    2.702025] tegradc 15200000.nvdisplay: tegra_dsi_bta 5
[    2.702028] tegradc 15200000.nvdisplay: tegra_dsi_bta end
[    2.702030] tegradc 15200000.nvdisplay: tegra_dsi_read_data_cmd read_fifo
[    2.707043] tegradc 15200000.nvdisplay: DSI RD_FIFO_CNT is zero (RD_DATA=0 dsi_status=0x400)
[    2.707046] tegradc 15200000.nvdisplay: DSI read fifo failure

adding explicit fifo read really really looks empty

this is /sys/kernel/debug/tegra_dsi/regs after a read, but during video mode

during video mode (after all read requests

15300000: 00000000 00000000-00000000 00000000
15300010: 00000000 00000000-00000000 00000000
15300020: 0000FC00 00000000-0000DA14 00000001
15300030: 00000000 00000000-00000000 00000023
15300040: 00003032 00000018-000001E0 00000000
15300050: FFFFFFFF 00001000-0000000D 00000000      D -> experimental VID_BTA_CONTROL
15300060: 00000000 00000000-00000000 00000000
15300070: 00000000 00000000-00000000 00000000
15300080: 00000000 00000000-00000000 40000208
15300090: 00000000 40000308-00000000 40000308
153000A0: 00000000 6C8B2B08-000003F3 40000308
153000B0: 00000000 6C8B2B08-000003F3 00000000
153000C0: 00000000 00000000-00000000 00000000
153000D0: 00320000 096000DF-000001DB 0F0F0000
153000E0: 00000000 00000000-00000000 00000000
153000F0: 06070704 040A0F03-000301FF F411060E
15300100: 00000000 00000000-00000000 00000000
15300110: 20001263 F3C72000-00000000 00000000
15300120: 00000000 00000000-00000000 00000000
15300130: 00030000 00000000-00000000 00000000
15300140: 00000000 00003333-00000000 00000000
15300150: 00000000 00000000-00000000 00000000
15300160: AF363EE6 EF8DB08C-0BB576EC C1F0D0EE
15300170: BE1EE474 FB990B2E-589F450C 00000000
15300180: 002B0080 00000000-00000000 00068800

15400000: 00000000 00000000-00000000 00000000
15400010: 00000000 00000000-00000000 00000000
15400020: 0000FC00 00000000-31FDC240 00000001
15400030: 00000000 00000000-00000000 00000023
15400040: 00003032 00000018-000001E0 00000000
15400050: FFFFFFFF 00001000-0000000D 00000000
15400060: 00000000 00000000-00000000 00000000
15400070: 00000000 00000000-00000000 00000000
15400080: 00000000 00000000-00000000 40000208
15400090: 00000000 40000308-00000000 40000308
154000A0: 00000000 6C8B2B08-000003F3 40000308
154000B0: 00000000 6C8B2B08-000003F3 00000000
154000C0: 00000000 00000000-00000000 00000000
154000D0: 00320000 096000DF-000001DB 0F0F0000
154000E0: 00000000 00000000-00000000 00000000
154000F0: 06070704 040A0F03-000301FF F411060E
15400100: 00000000 00000000-00000000 00000000
15400110: 20001263 F3C72000-00000000 00000000
15400120: 00000000 00000000-00000000 00000000
15400130: 00030000 00000000-00000000 00000000
15400140: 00000000 00003333-00000000 00000000
15400150: 00000000 00000000-00000000 00000000
15400160: 5EC42D10 CFA9522E-898D71AD FE740E88
15400170: 36ACC492 E8E43801-E3E4D00C 00000000
15400180: 00100080 00000000-00000000 00068800

DSI_INCR_SYNCPT_CNTRL                         | 0x001 | 0x00000000 |
DSI_INCR_SYNCPT_ERROR                         | 0x002 | 0x00000000 |
DSI_CTXSW                                     | 0x008 | 0x0000fc00 |
DSI_POWER_CONTROL                             | 0x00b | 0x00000001 |
DSI_INT_ENABLE                                | 0x00c | 0x00000000 |
DSI_HOST_DSI_CONTROL                          | 0x00f | 0x00000023 |
DSI_CONTROL                                   | 0x010 | 0x00003032 |
DSI_SOL_DELAY                                 | 0x011 | 0x00000018 |
DSI_MAX_THRESHOLD                             | 0x012 | 0x000001e0 |
DSI_TRIGGER                                   | 0x013 | 0x00000000 |
DSI_TX_CRC                                    | 0x014 | 0xffffffff |
DSI_STATUS                                    | 0x015 | 0x00001000 |
DSI_INIT_SEQ_CONTROL                          | 0x01a | 0x00000000 |
DSI_INIT_SEQ_DATA_0                           | 0x01b | 0x00000000 |
DSI_INIT_SEQ_DATA_1                           | 0x01c | 0x00000000 |
DSI_INIT_SEQ_DATA_2                           | 0x01d | 0x00000000 |
DSI_INIT_SEQ_DATA_3                           | 0x01e | 0x00000000 |
DSI_INIT_SEQ_DATA_4                           | 0x01f | 0x00000000 |
DSI_INIT_SEQ_DATA_5                           | 0x020 | 0x00000000 |
DSI_INIT_SEQ_DATA_6                           | 0x021 | 0x00000000 |
DSI_INIT_SEQ_DATA_7                           | 0x022 | 0x00000000 |
DSI_PKT_SEQ_0_LO                              | 0x023 | 0x40000208 |
DSI_PKT_SEQ_0_HI                              | 0x024 | 0x00000000 |
DSI_PKT_SEQ_1_LO                              | 0x025 | 0x40000308 |
DSI_PKT_SEQ_1_HI                              | 0x026 | 0x00000000 |
DSI_PKT_SEQ_2_LO                              | 0x027 | 0x40000308 |
DSI_PKT_SEQ_2_HI                              | 0x028 | 0x00000000 |
DSI_PKT_SEQ_3_LO                              | 0x029 | 0x6c8b2b08 |
DSI_PKT_SEQ_3_HI                              | 0x02a | 0x000003f3 |
DSI_PKT_SEQ_4_LO                              | 0x02b | 0x40000308 |
DSI_PKT_SEQ_4_HI                              | 0x02c | 0x00000000 |
DSI_PKT_SEQ_5_LO                              | 0x02d | 0x6c8b2b08 |
DSI_PKT_SEQ_5_HI                              | 0x02e | 0x000003f3 |
DSI_DCS_CMDS                                  | 0x033 | 0x00000000 |
DSI_PKT_LEN_0_1                               | 0x034 | 0x00320000 |
DSI_PKT_LEN_2_3                               | 0x035 | 0x096000df |
DSI_PKT_LEN_4_5                               | 0x036 | 0x000001db |
DSI_PKT_LEN_6_7                               | 0x037 | 0x0f0f0000 |
DSI_PHY_TIMING_0                              | 0x03c | 0x06070704 |
DSI_PHY_TIMING_1                              | 0x03d | 0x040a0f03 |
DSI_PHY_TIMING_2                              | 0x03e | 0x000301ff |
DSI_BTA_TIMING                                | 0x03f | 0xf411060e |
DSI_TIMEOUT_0                                 | 0x044 | 0x20001263 |
DSI_TIMEOUT_1                                 | 0x045 | 0xf3c72000 |
DSI_TO_TALLY                                  | 0x046 | 0x00000000 |
DSI_PAD_CONTROL                               | 0x04b | 0x00000000 |
DSI_PAD_CONTROL_CD                            | 0x04c | 0x00030000 |
DSI_PAD_CD_STATUS                             | 0x04d | 0x00000000 |
DSI_VID_MODE_CONTROL                          | 0x04e | 0x00000000 |
DSI_PAD_CONTROL_0_VS1                         | 0x04b | 0x00000000 |
DSI_PAD_CONTROL_CD_VS1                        | 0x04c | 0x00030000 |
DSI_PAD_CD_STATUS_VS1                         | 0x04d | 0x00000000 |
DSI_PAD_CONTROL_1_VS1                         | 0x04f | 0x00000000 |
DSI_PAD_CONTROL_2_VS1                         | 0x050 | 0x00000000 |
DSI_PAD_CONTROL_3_VS1                         | 0x051 | 0x00003333 |
DSI_PAD_CONTROL_4_VS1                         | 0x052 | 0x00000000 |
DSI_GANGED_MODE_CONTROL                       | 0x053 | 0x00000000 |
DSI_GANGED_MODE_START                         | 0x054 | 0x00000000 |
DSI_GANGED_MODE_SIZE                          | 0x055 | 0x00000000 |

here is a bit of the panel dts:

  26                         panel_s_wuxga_8_0: panel-s-wuxga-8-0 {
  27                                 status = "disabled";
  28                                 compatible = "s,wuxga-8-0";
  29                                 nvidia,dsi-instance = <DSI_INSTANCE_0>;
  30                                 nvidia,dsi-n-data-lanes = <4>;
  31                                 nvidia,dsi-pixel-format = <TEGRA_DSI_PIXEL_FORMAT_24BIT_P>;
  32                                 nvidia,dsi-refresh-rate = <60>;
  33                                 nvidia,dsi-video-data-type = <TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE>;
  34                                 nvidia,dsi-video-clock-mode = <TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS>; //TEGRA_DSI_VIDEO_CLOCK_TX_ONLY
  35                                 nvidia,dsi-lp00-pre-panel-wakeup = <TEGRA_DSI_DISABLE>;
  36                                 /*nvidia,enable-hs-clk-in-lp-mode;*/
  37                                 nvidia,dsi-video-burst-mode = <TEGRA_DSI_VIDEO_NONE_BURST_MODE>;
  38                                 /*
  39                                 nvidia,dsi-ganged-type = <TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT>;
  40                                 nvidia,dsi-ganged-swap-links = <1>;
  41                                 nvidia,dsi-ganged-write-to-all-links = <1>;
  42                                 */
  43 
  44                                 /*nvidia,dsi-phy-hsdexit = <123>; /* dsi phy timing, t_hsdexit_ns.*/
  45                                 /*nvidia,dsi-phy-hstrail = <85>; /* dsi phy timing, t_hstrail_ns.*/
  46                                 /*nvidia,dsi-phy-datzero = <170>; /* dsi phy timing, t_datzero_ns.*/
  47                                 /*nvidia,dsi-phy-hsprepare = <57>; /* dsi phy timing, t_hsprepare_ns.*/
  48 
  49                                 /*nvidia,dsi-phy-clktrail = <1>; /* dsi phy timing, t_clktrail_ns.*/
  50                                 /*nvidia,dsi-phy-clkpost = <1>; /* dsi phy timing, t_clkpost_ns.*/
  51                                 /*nvidia,dsi-phy-clkzero = <1>; /* dsi phy timing, t_clkzero_ns.*/
  52                                 /*nvidia,dsi-phy-tlpx = <1>; /* dsi phy timing, t_tlpx_ns.*/
  53                                 /*nvidia,dsi-phy-clkprepare = <1>; /* dsi phy timing, t_clkprepare_ns.*/
  54                                 /*nvidia,dsi-phy-clkpre = <1>; /* dsi phy timing, t_clkpre_ns.*/
  55                                 /*nvidia,dsi-phy-wakeup = <1>; /* dsi phy timing, t_wakeup_ns.*/
  56 
  57                                 nvidia,dsi-phy-tpktbta = <4000>; /* dsi phy timing, t_taget_ns.*/
  58                                 /* nvidia,dsi-phy-taget = <200>; /* dsi phy timing, t_taget_ns.*/
  59                                 /* nvidia,dsi-phy-tasure = <400>; /* dsi phy timing, t_tasure_ns.*/
  60                                 /* nvidia,dsi-phy-tago = <600>; /* dsi phy timing, t_tago_ns. */
  61 
  62                                 nvidia,dsi-controller-vs = <DSI_VS_1>;
  63                                 nvidia,dsi-virtual-channel = <TEGRA_DSI_VIRTUAL_CHANNEL_0>;
  64                                 nvidia,dsi-panel-reset = <TEGRA_DSI_ENABLE>;
  65                                 nvidia,dsi-ulpm-not-support = <TEGRA_DSI_DISABLE>;
  66                                 nvidia,dsi-suspend-stop-stream-late = <TEGRA_DSI_ENABLE>;
  67                                 nvidia,dsi-power-saving-suspend = <TEGRA_DSI_DISABLE>;
  68                                 nvidia,default_color_space = <1>;       /*default color profile:adobeRGB*/
  69                                 nvidia,dsi-init-cmd =
...
 329                                 nvidia,dsi-pkt-seq =
 330                                                         <CMD_VS LEN_SHORT PKT_LP LINE_STOP>,
 331                                                         <CMD_HS LEN_SHORT PKT_LP LINE_STOP>,
 332                                                         <CMD_HS LEN_SHORT PKT_LP LINE_STOP>,
 333                                                         <CMD_HS LEN_SHORT CMD_BLNK LEN_HBP CMD_BLNK LEN_SHORT CMD_RGB_24BPP LEN_HACTIVE3 PKT_LP LINE_STOP>,
 334                                                         <CMD_HS LEN_SHORT PKT_LP LINE_STOP>,
 335                                                         <CMD_HS LEN_SHORT CMD_BLNK LEN_HBP CMD_BLNK LEN_SHORT CMD_RGB_24BPP LEN_HACTIVE3 PKT_LP LINE_STOP>;
 336 

we have tried a lot of different things:
-trying to control the BTA through PKT_BTA instead of IMM_BTA, to delay the display response to generate time for jetson to read response by 4us ( nvidia,dsi-phy-tpktbta = <4000>;)
-tried VID_BTA_CONTROL to continuously set and/or change the BTA line (in command mode this will do nothing we think).
-tried all sorts of nvidia,dsi-pkt-seq
-tried TearingEffect 0x35
-tried changing the read function to change max_threshold and trigger on fifo_level
-tried to change dsi-ulpm-not-support
-tried dsi-video-clock-mode continuous and tx_only
-tried syncpt OP_MODE | RD_MODE , but then the kernel deadlocks) (we do not know how syncpts work)
-measured the voltages for logical 0, and logical 1 are OK

so the BTA handover to display seems to work,
response from display is OK,
last part of of display response seems to be a BTA,
but after that bus handover to jetson it seems to timeout 218ms as if
-jetson has not seen the response, causing syncpt timeeout
-or jetson waits for a different syncpt causing syncpt timeout

so my simplest questions would be:
does the function dsi.c:tegra_dsi_read_data() work?
and what variables should we look at that could cause fifo to remain empty and syncpt to timeout?

1 Like

as a clarification we have 2 very different platforms, but with the same display:
-a platform with: jetson tx2->mipi-dsi->display connection where the problem occurs
-a different platform: TI am335x → lvds → Toshiba → mipi-dsi → display (same display) with no problem

Hi,

Could you share what you have added to the device tree and current dmesg?

Please follow the sample panel driver and device tree to enable panel.

Please also refer to other user’s post here. He enabled DSI recently. Though it is on the TX2-NX.

Hi , thanks for the reply.

our current status: our panel works, however we cannot read any display register.

I have looked at most forum posts about DSI, these are about bringing up the DSI. Almost none are about reading registers from the DSI Display.
There is one forum post that is closer to our problem, but also asks the question if the does the tegra_dsi_read_data() function work? (no clear answer there)

we started from the stock panel-s-wuxga-8-0.dtsi definition , and added the init-cmd and pkt-seq. a segment is listed in the first post (I have now attached the full panel file, and a portion of the dts that includes it)

panel-s-wuxga-8-0.dtsi (55.4 KB)
part-of-display-includes-panel-s-wuxga.dts (4.3 KB)
console-read_panel.txt (2.2 KB)
console-bootup-logs.txt (93.4 KB)

do you know or can you verify that the function dsi.c:tegra_dsi_read_data() works (on a stock jetson devkit tx2)?

Sorry that we cannot guarantee whether that function would work or not.

Is there something you can do to verify that this function could work?

we have been analyzing this function, and been looking into the TRM, to find out how this read function should work. in the documentation around the SYNCPT , the descriptions are a little bit short, is there more documentation around this (DSI_INCR_SYNCPT_0 page 2562 ) OP_RDDONE.
or can you explain how this should work?

looking at the TRM 24.8.15.1 the MAX_THRESHOLD and TRIGGER FIFO_LEVEL are not used in this function, shoudl this be used/implemented?

1 Like

by saying “not guaranteed” does that mean some hardware is broken?
do you have errata on this topic and which jetsons are affected by this?

No, I didn’t mean that.

It is more like this function wasn’t tested for like few years since it was added. We cannot guarantee whether this is still working or not.

Following the procedure over TRM shall make things work.

we cannot seem to get it to work. we are abandoning any form of read function.

Same problem here. I have tried to read a register according to TRM without success.
WayneWWW could you please provide some code ?