DSI output wrong pixel clock when defining multiple display timings

Robotics & Edge Computing Jetson & Embedded Systems Jetson TX2
1

Hi all,

I’m working with MIPI-DSI output of TX2 and need to define multiple display timings for my panel.
I have tested several resolutions individually and they all work fine, however, if I define all of then at the same time under the display-timings node, when I run xrandr, all the resolutions are reported correctly but all of them use the pixel clock defined for the first timing on the list. I tried adding the timings in different orders and in all the cases the modes are reported using the clock defined for the first one (the clock-frequency property seems to be ignored for the 2nd, 3rd, … mode on the list).

Here is how I’m defining the display timings:

display-timings {
          640x480-60Hz {
            clock-frequency = <25200000>;
            hactive = <640>;
            vactive = <480>;
            hfront-porch = <16>;
            hback-porch = <48>;
            hsync-len = <96>;
            vfront-porch = <10>;
            vback-porch = <33>;
            vsync-len = <2>;
            nvidia,h-ref-to-sync = <1>;
            nvidia,v-ref-to-sync = <1>;
          };
          640x400-60Hz {
            clock-frequency = <21552000>;
            hactive = <640>;
            vactive = <400>;
            hfront-porch = <16>;
            hback-porch = <48>;
            hsync-len = <96>;
            vfront-porch = <12>;
            vback-porch = <35>;
            vsync-len = <2>;
            nvidia,h-ref-to-sync = <1>;
            nvidia,v-ref-to-sync = <1>;
          };
          640x360-60Hz {
            clock-frequency = <18816000>;
            hactive = <640>;
            vactive = <360>;
            hfront-porch = <16>;
            hback-porch = <48>;
            hsync-len = <96>;
            vfront-porch = <27>;
            vback-porch = <3>;
            vsync-len = <2>;
            nvidia,h-ref-to-sync = <1>;
            nvidia,v-ref-to-sync = <1>;
          };
          720x480-60Hz {
            clock-frequency = <27027000>;
            hactive = <720>;
            vactive = <480>;
            hfront-porch = <16>;
            hback-porch = <60>;
            hsync-len = <62>;
            vfront-porch = <9>;
            vback-porch = <30>;
            vsync-len = <6>;
            nvidia,h-ref-to-sync = <1>;
            nvidia,v-ref-to-sync = <1>;
          };
};

And here is the output of xrandr:

ConnectorType: Panel 
  640x480 (0x18d) 25.200MHz *current +preferred
        h: width   640 start  656 end  752 total  800 skew    0 clock  31.50KHz
        v: height  480 start  490 end  492 total  525           clock  60.00Hz
  720x480 (0x18e) 25.200MHz
        h: width   720 start  736 end  798 total  858 skew    0 clock  29.37KHz
        v: height  480 start  489 end  495 total  525           clock  55.94Hz
  640x400 (0x18f) 25.200MHz
        h: width   640 start  656 end  752 total  800 skew    0 clock  31.50KHz
        v: height  400 start  412 end  414 total  449           clock  70.16Hz
  640x360 (0x190) 25.200MHz
        h: width   640 start  656 end  752 total  800 skew    0 clock  31.50KHz
        v: height  360 start  387 end  389 total  392           clock  80.36Hz

As you can see, the resolutions are fine but the clocks are all the same eventhough they are properly defined in the device tree.
I also tested this in a TX1 with the same results.

Has anyone seen this issue before?

I’m using Jetpack 3.2 (L4T 28.2).

Any help will be really appreciated.

  • Edison
2

Edison_F_A,

I believe it is due to the dsi driver can only handle one display-timings per time.

As I know, we don’t have dts that has multiple display-timings.

3

Hi Wayne,

Thanks a lot for you reply. Turns out I just found what was causing the issue.
In fb.c, in tegra_fb_register, when all the video modes are added based on the list of timings provided in the device tree, for some reason the pclk is overwritten with the value of the first element on the list, causing all the modes to be reported with the same clock.

Just in case it is useful for anyone here is how I fixed the issue.

--- sources.orig/kernel/display/drivers/video/tegra/fb.c
+++ sources/kernel/display/drivers/video/tegra/fb.c
@@ -1238,7 +1238,7 @@ struct tegra_fb_info *tegra_fb_register(
 		struct tegra_dc_mode mode = dc->out->modes[mode_idx];
 		struct fb_videomode vmode;
 
-		mode.pclk = dc->mode.pclk;
+		// mode.pclk = dc->mode.pclk; /*Why this line?*/
 
 		if (mode.pclk > 1000) {
 			tegra_dc_to_fb_videomode(&vmode, &mode);

I tested with several display-timings defined and it worked fine.

  • Edison
4

Edison_F_A,

Thanks for pointing out this. I wonder why other display interface didn’t hit such error…
I’ll check it.

5

It seems this is an issue that only DSI would hit since HDMI and DP would have mode list from edid instead of reading dts.

Thanks for your help. I’ll report this to internal team.

6

BTW, Does your panel support multiple modes?

7

Hi Wayne,

Yes, I’m using a DSI to HDMI converter that supports multiple modes.

  • Edison