Hello!
We’re observing an FCC emissions failure which appears related to the MIPI DSI from our TX2 NX to our LCD display. We’re configured as 2 lane MIPI on our custom carrier board. We are working on electrical/mechanical mitigations but also want to explore firmware settings to confirm we understand the root cause.
The radio emission we see is a spur at 471.0MHz, which appears to be the 3rd harmonic of the DSI high-speed CLK (measured at 157.0MHz with our oscilloscope). This clock is derived from PLLD, which is at 313.992 MHz.
Can we please have your assistance to change the parameters of the MIPI CLK system? Some ideas we’d like to try:
1)changing refresh rate to a slower one
2)Enabling Spread Spectrum on PLLD which creates the MIPI DSI clock (Parker SoC TRM says PLL D supports spread spectrum)
3)changing MIPI modes to reduce the duty-cycle of the clock (eg: transition to LP mode more often).
We’ve tried enabling burst modes, but that had no effect on the radio emissions, and the DSI CLK signal didn’t change on the oscilloscope. Also while we have the refresh rate set to 30Hz, the period of the DSI CLK signal appears to be 60Hz, so something in our settings may be getting overwritten. Here are our settings:
panel_v_wsvga_7_0: panel-v-wsvga-7-0 {
status = "disabled";
compatible = "v,wsvga-7-0";
nvidia,dsi-instance = <DSI_INSTANCE_0>;
nvidia,dsi-n-data-lanes = <2>;
nvidia,dsi-pixel-format = <TEGRA_DSI_PIXEL_FORMAT_24BIT_P>;
nvidia,dsi-refresh-rate = <30>;
nvidia,dsi-video-data-type = <TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE>;
nvidia,dsi-video-clock-mode = <TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS>;
nvidia,dsi-video-burst-mode = <TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END>;
nvidia,dsi-virtual-channel = <TEGRA_DSI_VIRTUAL_CHANNEL_0>;
nvidia,dsi-panel-reset = <TEGRA_DSI_ENABLE>;
nvidia,dsi-ulpm-not-support = <TEGRA_DSI_ENABLE>;
//nvidia,dsi-suspend-stop-stream-late = <TEGRA_DSI_ENABLE>;
nvidia,dsi-power-saving-suspend = <TEGRA_DSI_ENABLE>;
nvidia,default_color_space = <1>; /*default color profile:adobeRGB*/
nvidia,dsi-init-cmd =
/* Long Packet: <PACKETTYPE[u8] COMMANDID[u8] PAYLOADCOUNT[u16] ECC[u8] PAYLOAD[..] CHECKSUM[u16]> */
/* Short Packet: <PACKETTYPE[u8] COMMANDID[u8] DATA0[u8] DATA1[u8] ECC[u8]> */
/* For DSI packets each DT cell is interpreted as u8 not u32 */
<TEGRA_DSI_DELAY_MS 160>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0xB2 0x10 0x0>, /* Configure for 2 lanes */
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x80 0x5B 0x0>, /* Gamma Control Register G2R/G1R */
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x81 0x47 0x0>, /* Gamma Control Register G4R/G3R */
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x82 0x84 0x0>, /* Gamma Control Register G6R/G5R */
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x83 0x88 0x0>, /* Gamma Control Register G8R/G7R */
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x84 0x88 0x0>, /* Gamma Control Register G10R/G9R */
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x85 0x23 0x0>, /* Gamma Control Register G12R/G11R */
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_1_PARAM 0x86 0xB6 0x0>, /* Gamma Control Register G14R/G13R */
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_EXIT_SLEEP_MODE 0x0 0x0>, /* Exit sleep mode */
<TEGRA_DSI_DELAY_MS 120>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_SET_DISPLAY_ON 0x0 0x0>, /* Display On */
<TEGRA_DSI_DELAY_MS 20>;
nvidia,dsi-n-init-cmd = <13>;
nvidia,dsi-suspend-cmd =
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_SET_DISPLAY_OFF 0x0 0x0>,
<TEGRA_DSI_SEND_FRAME 3>,
<TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_ENTER_SLEEP_MODE 0x0 0x0>,
<TEGRA_DSI_SEND_FRAME 10>;
nvidia,dsi-n-suspend-cmd = <4>;
disp-default-out {
nvidia,out-type = <TEGRA_DC_OUT_DSI>;
nvidia,out-width = <154>;
nvidia,out-height = <86>;
nvidia,out-flags = <TEGRA_DC_OUT_CONTINUOUS_MODE>;
nvidia,out-parent-clk = "pll_d_out0";
nvidia,out-xres = <1024>;
nvidia,out-yres = <600>;
};
display-timings {
1024x600-32-30Hz {
clock-frequency = <25653000>;
hactive = <1024>;
vactive = <600>;
hfront-porch = <80>;
hback-porch = <160>;
hsync-len = <80>;
vfront-porch = <12>;
vback-porch = <23>;
vsync-len = <13>;
nvidia,h-ref-to-sync = <1>;
nvidia,v-ref-to-sync = <1>;
};
};
Thanks your your help,
Mike - Electrical Engineering team