We would like to drive two display panels in two physically different DSI interfaces. Reading around, it doesn’t seem clear if this setup is supported.
Currently we have one DSI and one HDMI display working fine.
Are there any device tree examples I can look at?
Please note that TX2 supports only up to 3 head display, so only DSI+DSI+HDMI is possible for you.
This user has enabled 2 DSI. Although your usecase is different from his, you can still leverage his work because he can enable 2 DSI panel separately.
Thanks for the reply WayneWWW.
Please let me check I’ve understood correctly. After looking at the driver code it seems I can only have one dsi node, “/host1x/dsi”, and only a single logical panel within that node.
To get two outputs over the two DSI interfaces, I would need to:
- Create a logical panel with a total width of the two physical displays (say, 2*1920 by 1080)
- Configure it for left/right ganged mode (with no overlap)
- Expect DSI output line counts to be the same on both DSI busses?
In fact if that is the case then that might be quite acceptable in our case, as we fill external frame buffers, and have an external device output only the proportion of that frame buffers that we need.
Are the left and right parts of each line transmitted simultaneously in this case? Our maximum permissible DSI clock speed is only just over what is required to transmit 1920x1080 pixels at 30Hz refresh.
You can use dsi-instance to control which panel you want to use.
I’m making some progress on this. I have used ganged mode left/right with split link DSIA/DSIB.
Initially this didn’t work, as the DSI driver in the kernel drops the specified HSA, HBP and HFP timings and makes up new numbers which maintain the VS and HS timings overall.
But it sets HSA = 0, HBP = 0 and HFP = (total line length - the active video length)
Technically this is legal, but might not work with all possible panels. Not ours, for example.
Ideally you would have display timings for each DSI link in the device-tree. For our case (two panels) I am patching the DSI driver to take the HSA, HSB and HFP from the single display timings node and (just like the h_active length) dividing by 2 to get the timings for use on each panel. This should at least allow a pair of matched panels to work.
This appears to be good enough to get our case working, though there are still some signal stability issues I’m working through.
I’m only using a single nvdisplay to drive this. I still have two left. Doesn’t that imply I can get two identical DSI displays (host1x/dsi), one HDMI display (host1x/sor) and one DP display (host1x/sor1), for a total of four outputs? I don’t need four, I’m just curious.
So you’ve enabled to use single DSI controller to use split link with ganged mode??
Could you share how your device tree looks like?
Good question. In fact I did have both split and ganged enabled. Actually, it works with either enabled. Let me stress though, that this only works for panels with the same pixel resolutions and timing requirements.
The panel settings for split-link in the DSI node look like:
nvidia,dsi-panel-reset = <0>;
nvidia,panel-rst-gpio = <0x12 0x7b 0x1>;
nvidia,dsi-refresh-rate = <30>;
nvidia,dsi-video-burst-mode = <1>;
nvidia,dsi-virtual-channel = <0x0>;
nvidia,dsi-ganged-type = <0>;
nvidia,dsi-ganged-write-to-all-links = <0>;
nvidia,dsi-split-link-type = <1>;
nvidia,default_color_space = <0x0>;
nvidia,dsi-video-data-type = <0x0>;
nvidia,dsi-suspend-stop-stream-late = <0x1>;
nvidia,dsi-controller-vs = <0x1>;
nvidia,dsi-power-saving-suspend = <1>;
nvidia,dsi-instance = <0>;
nvidia,dsi-ulpm-not-support = <0x1>;
nvidia,dsi-video-clock-mode = <0>;
nvidia,enable-hs-clk-in-lp-mode = <1>;
nvidia,dsi-pixel-format = <3>;
nvidia,dsi-n-data-lanes = <8>;
nvidia,en-vmm-vpp-with-i2c-config = <1>;
Once I’ve cleaned out the redundant code in dsi.c, I’ll share a patch for that. Not that I think it is a perfect solution, but it does allow me to communicate required timings for match panels. Mismatched panels will not work, but the rest of the code assumes the pixel widths are equal anyway, so the patch doesn’t make the situation any worse.
Here (attached) is the cleaned up patch code for dsi.c. This is only required for panels the can’t work with hsa and hbp set to 0. With the patch applied you can still set hsa and hbp to zero in the display-timings DTS node.
Note that the display-timings hsa, hbp and hfp timings are divided by the number of display links you have (1, 2 ganged/split_DSI_A_B/split_DSI_C_D or 4 split_DSI_A_B_C_D).
Ganged overlapping modes do the same as the non-overlapped modes of hsa, hbp and hfp - that’s to say, it’s identical to the above description.
The original dsi.c, was the one from 28.2-DP1. I’ll be porting this to 28.2.1 very soon (if it’s any different).
dsi.c.28.2-rc.diff.txt (4.04 KB)