problematic signal layout for the lanes coming from HEAD0
Sorry that I cannot get it. Are you trying to say hardware design problem?
There is no “lanes coming out from HEAD0”.
HEAD0 is just a virtual concept. It does not mean any physical pin.
For example, SOR0 node which represent DP0 pins can be assigned to HEAD0. And it can be assigned to HEAD1 too. In each case (HEAD0/HEAD1), the hardware connection are same but just on different display controller. Different display controller means it is possible has different software configuration.
Thus, what you are trying to do is
You set DSI-C to either head0 or head 1 and the result are different. I would say this may be just because some other software configuration are different…
And if you can understand above, then “trying to put DSI-C to HEAD0 instead of DSI-A” is also not a very precise statement. What you really do is “putting dsi contoller as dc-connector to headX”. And what you need to do next is configure the dsi node to let it output signal from DSI-C.