DSI in non-ganged mode

Hello
I’m using “panel-s-wuxga-8-0.dtsi” to send DSI video to a FPGA. But it is seems to be configured as 4-lane ganged mode.
I need DSI in non-ganged mode. When I commented these lines :
//nvidia,dsi-ganged-type = <TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT>;
//nvidia,dsi-ganged-swap-links = <1>;
//nvidia,dsi-ganged-write-to-all-links = <1>;
And I check the ِِDSI signals in the FPGA, It seems that the video is sending in a non-split and non-ganged form TX2 and its dimensions were not halved (not left-right and not even-odd)
But there is no 0x21 (CMD_HS) in first of each line in received stream and I can’t use it.
What should I do? Is there any tested configuration for this?

Hi,
This topic contradicts with


Please clarify you need ganged or non-ganged mode.

I need non-ganged mode.

I need non-ganged mode. Any sample dts for non-ganged.

Please guide me!
I need this two stream Simultaneously:
Camera 1 => 4lanes DSI
Camera 2 => 4lanes DSI
I am confused. What is difference between
ganged and non-ganged and split and Dual-link mode?!!

Hi,

Currently we only support/verify 8-lane on single DSI controller case as panel-s-wuxga-8-0.dtsi.
There are some problems in driver so cannot run with two controllers.

To know the dts properties, you could refer to below page.

Ok
Now panel-s-wuxga-8-0.dtsi is configured as splited? or ganged? dual display or dual-link one display?

Hi,

It is ganged mode with dual link.

1 Like

Thanks. But I don’t know difference between ganged and non-ganged!

What is your final usecase? Single display or multiple DSI display?

I need two stream Simultaneously :
Camera 1 => 4lanes DSI => Display 1
Camera 2 => 4lanes DSI => Display 2

Hi,

Unfortunately, the second 4-lanes DSI to display 2 is not supported in our software driver.

OK,
Now I want to change panel-s-wuxga-8-0.dtsi for 4-lane.
Camera 1 => 4-lane DSI-A => Display 1
What should I do? When I do this change :
nvidia,dsi-n-data-lanes = <8>; to nvidia,dsi-n-data-lanes = <4>;
then DSI signal is only on DSI-A (2-lane) !!! I check the received signal with fpga and apparently only the right half of the image is sent

Hi,

Could you remove below in the dts?

                              nvidia,dsi-ganged-type = <TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT>;
                               nvidia,dsi-ganged-swap-links = <1>;
                               nvidia,dsi-ganged-write-to-all-links = <1>;

Yes. This is result : tegradc 15200000.nvdisplay: dsi: video fifo underflow. Resetting flag
Of course, this change caused to have a signal on all four lanes of DSI-A. But apparently these signals are not healthy video.
Maybe I’m making a mistake in receiving the video with fpga. I will be here again after testing and review.
Thanks