Problems enabling DSI on TX2

We have a system using a TX2 on a custom carrier where we want to be able
to drive 4 monitors. The 2 HDMI monitors are working fine. Our X-based
application works across the two monitors.

Next step is to enable some CSI output so the hardware dev can start testing his hardware.
I modified our dts based on postings here and the devicetree/bindings information
in the kernel documentation. In the top-level dts for this board I have enabled
dsi and a panel with the following:

#include "tegra186-quill-p3310-1000-c03-00-dsi-hdmi-hdmi.dts"

    / {
    	nvidia,dtsfilename = __FILE__;

    	host1x {
            dsi {
                status = "ok";
                panel-s-wqxga-10-1 {
                    status = "ok";
                };
            };
    	};
    };

The decompiled dtb has the detailed information for the dsi seems to show this (… indicates removed blocks)

dsi {
			compatible = "nvidia,tegra186-dsi";
			reg = <0x0 0x15300000 0x0 0x40000 0x0 0x15400000 0x0 0x40000 0x0 0x15900000 0x0 0x40000 0x0 0x15940000 0x0 0x40000 0x0 0x15880000 0x0 0x10000>;
			clocks = <0xbc 0xd 0x73 0xd 0x75 0xd 0x76 0xd 0x77 0xd 0xe7 0xd 0xe8 0xd 0xe9 0xd 0xea>;
			clock-names = "clk32k_in", "dsi", "dsia_lp", "dsib", "dsib_lp", "dsic", "dsic_lp", "dsid", "dsid_lp";
			resets = <0xd 0x6 0xd 0x7 0xd 0x3f 0xd 0x40 0xd 0x91>;
			reset-names = "dsia", "dsib", "dsic", "dsid", "dsi_padctrl";
			nvidia,enable-hs-clk-in-lp-mode = <0x1>;
			pad-controllers = <0x10 0xf 0x10 0x10 0x10 0x11 0x10 0x12>;
			pad-names = "dsia", "dsib", "dsic", "dsid";
			status = "ok";
			nvidia,dsi-controller-vs = <0x1>;

			prod-settings {
				#prod-cells = <0x3>;

				dsi-padctrl-prod {
					prod = <0x24 0x3f0fc3f 0x0 0x28 0x333333 0x0 0x30 0xffffff 0x0 0x34 0xffffff 0x777777 0x54 0x3f0fc3f 0x0 0x58 0x333333 0x0 0x60 0xffffff 0x0 0x64 0xffffff 0x777777 0x84 0x3f0fc3f 0x0 0x88 0x333333 0x0 0x90 0xffffff 0x0 0x94 0xffffff 0x777777 0xb4 0x3f0fc3f 0x0 0xb8 0x333333 0x0 0xc0 0xffffff 0x0 0xc4 0xffffff 0x777777>;
				};
			};

...
			panel-s-wqxga-10-1 {
				status = "ok";
				compatible = "s,wqxga-10-1";
				nvidia,dsi-instance = <0x0>;
				nvidia,dsi-n-data-lanes = <0x8>;
				nvidia,dsi-pixel-format = <0x3>;
				nvidia,dsi-refresh-rate = <0x3d>;
				nvidia,dsi-rated-refresh-rate = <0x3c>;
				nvidia,dsi-te-polarity-low = <0x1>;
...

And these nodes show up under

/sys/firmware/devicetree/base/host1x/dsi

So that all seems correct.

A dsi device is created

/sys/devices/13e10000.host1x/15300000.dsi

But no screen or monitor is detected by xrandr, and there are only the two /dev/fb[01] entries
for the HDMI monitors. There is no dsi activity in the kernel log except for this one
power message:

[    0.317764] avdd_dsi_csi: 1200 mV

Any ideas how I can get this working so we can continue to debug the hardware?

Thanks in advance,

Cary

I guess panel selection may have some problem.

Could you add debug message in panel-s-wqxga-10-1 driver to check if it is enabled? I guess it is not.

Thanks, that at least gave me a starting point to go through how the driver is set up.

I found one problem was that the display controller @15200000 that is connected to the dsi
outputs in the dtb wasn’t enabled. My DTS is now:

#include "tegra186-quill-p3310-1000-c03-00-dsi-hdmi-hdmi.dts"

    / {
    	nvidia,dtsfilename = __FILE__;

    	host1x {


            nvdisplay@15200000 {
                status = "ok";
            };

            dsi {
                status = "ok";
                panel-s-wqxga-10-1 {
                    status = "ok";
                };
            };
    	};
    };

This is now recognized by the X driver, xrandr shows the monitors laid out left-to-right as follows:

DSI-0 connected primary 2560x1600+0+0 (normal left inverted right x axis y axis) 0mm x 0mm
   2560x1600     61.01*+
HDMI-0 connected 1920x1080+2560+0 (normal left inverted right x axis y axis) 480mm x 270mm
   1920x1080     60.00*+  50.00  
 ...
HDMI-1 connected 1360x768+4480+0 (normal left inverted right x axis y axis) 410mm x 230mm
   1360x768      60.02*+
...

Now our hardware engineer will have to take a look at the conversion chip configuration.

This still isn’t exactly right, we want to be able to drive two DSI outputs, not one. Any
idea what I would have to do to split that display controller between 2 dsi outputs?

Thanks for the help.

Cary

HI cobrien,

That may be the problem. Do you want to enable more than 3 displays on TX2? We can only support up to 3 heads.

The requirement is to drive four monitors, 2 via HDMI (working), and 2 via the DSI outputs.

The Parker TRM Section 24.3 seems to suggest it may be possible to drive 2 DSI outputs with one display head. Is this possible? If so, what would be the dtb configuration required to set it up?

Hi cobrien,

May I ask which part points out this combination? Is this one? “the output from any head can be routed to either SOR or to the DSI encoder. It is possible for one head to drive two SORs simultaneously…”

In fact, TRM only indicated the hardware possibility. However, we may not implement in sw stack.

In the TRM Section 24.1 “Features” it says

“Two DSI Controllers, each drives the data on the respective D-PHY Lanes”

In section 24.3 section “System Level Architecture” it says

“A pixel stream from a single display head is
sent to both DSI controllers where each controller captures only the active pixels it will drive over its DSI lanes. The other
display head input is ignored by the DSI controllers. A common PLL is used to derive the pixel clock for the shared video stream
along with the byte clocks used to drive the data over the 2 DSI links. Each DSI controller can drive up to 4 lanes clocked by a
common PLL. The common clock source will avoid any skew between DSI controllers.”

I suspect this is what they were looking at when they decided this would be possible.

I understand there may be restrictions, i.e appearing as a single device spanning both
monitors, the resolution and pixel rates having to match, and so on. We have a fair amount
of flexibility in the DSI->HDMI conversion circuitry at this point.

Any insight into what our options might be in this area would be appreciated.

Thanks,

Cary

Hi cobrien,

Thanks for pointing out. I think we are talking about different issue here. Your reference is under the section “MIPI-DSI” which is the capability of TX2 DSI hardware. However, I am talking about display controller (DC) in software stack.

TX2 currently supports up to 3 DCs, as a result you can only see 3 display when using xrandr even under the case you enable 4 display in the same time.

We’re continuing to work with getting the DSI output to work, our hardware group is going
to investigate what the output options are. So far I’ve made some progress working through
the device tree settings and tracing the code.

During startup and when starting Xorg or running xrandr (where DSI-0 shows up and seems
to operate correctly) we get the expected clock and data signals out of the DSI video output.
At all other times there is no clock or data.

I looked through the registers shown in /sys/kernel/debug/tegra_dsi/regs and it seems
as if the power is being turned off.

Usually it’s 0:

DSI_POWER_CONTROL                             | 0x00b | 0x00000000 |

But if I start xorg, or run xrandr it is turned on for a bit

DSI_POWER_CONTROL                             | 0x00b | 0x00000001 |

I’ve been trying to track down why this would happen. Is there some sort of panel
detection or overall panel enable I’m missing?

Thanks in advance,

Cary

Hi cobrien,

Is your question based on single DSI case?

The power control should not only happen when using xorg. Panel should be powered on even when no X11 usecase.

If you are still using our display driver stack, any activity could be seen in fb.c, dc.c and your own panel driver (power sequence).

Sorry for the delay, out on vacation.

We are trying to sort out just getting DSI-0 working, so just one DSI output. We
will try and investigate splitting this across two displays later.

After power up I don’t see any DSI activity, and the DSI_POWER_CONTROL reads back as 0.

If I start Xorg, I get bursts of activity, but when it’s finished, again DSI_POWER_CONTROL
is back to 0.

I will investigate the panel driver.

Thanks,

Cary

I found out the dsi.panel.displdefault-out.nvidia,out-flags had to be set to continuous mode:

dsi {
                status = "ok";
                panel-s-wqxga-10-1 {
                    status = "ok";
                    nvidia,dsi-video-data-type = <0x0>; /* VIDEO_MODE (not COMMAND_MODE) */
                    nvidia,dsi-video-clock-mode = <0x0>; /* CLOCK MODE CONTINUOUS */
                    nvidia,dsi-video-burst-mode = <0x3>; /* TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED */
                    /* nvidia,dsi-video-burst-mode = <0x0>; /* TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END */
                    nvidia,dsi-power-saving-suspend = <0x0>;

				disp-default-out {
					nvidia,out-type = <0x2>;
					nvidia,out-width = <0xd8>;
					nvidia,out-height = <0x87>;
					nvidia,out-flags = <0x00>; /* Continious Mode?? (was 0x20 one shot LP Mode) */
					nvidia,out-parent-clk = "pll_d";
					nvidia,out-xres = <0xa00>;
					nvidia,out-yres = <0x640>;
					nvidia,out-rotation = <0xb4>;
				};
                    
                };
            };

Now there’s a constant clock and data output and our hardware engineer is looking at the DSI -> HDMI conversion circuitry.