TX2 DSI LCD Panel Bringup Issues

Robotics & Edge Computing Jetson & Embedded Systems Jetson TX2
1

Hi all,

I’ve been trying to get a DSI lcd panel (720x720, 4") up and running on a P3489 with our custom carrier boards, and am having a few issues.

I can see the panel in Ubuntu’s display manager, xrandr, and fbset as expected, but am trying to fix the following issue:

The first horizontal line of the display seems to repeat for all vertical lines, so while I see some activity on the display, it is all just straight lines of different colors spanning top to bottom.

I would expect the below image to show the ubuntu desktop shortcuts bar on the left hand side, and a black desktop background:

dsi-bringup-1
dsi-bringup-1519×640 51.4 KB

I’ve tried my best to replicate the panel’s datasheet specs in the device tree, which mentions clock on TX only, and burst mode, but I always see “Forcing continuous clock”, and picking one of the burst modes makes the panel fade in and out continuously.

Hoping someone who’s successfully brought up a DSI panel and/or nvidia folks can point me in the right direction here. Thanks in advance!

Device Tree snippet:

/ {
host1x {
dsi {
panel_tf_720_4_0: panel-tf-720-4-0 {
status = “okay”;
compatible = “tf,720-4-0”;
nvidia,panel-rst-gpio = <&tegra_main_gpio TEGRA_MAIN_GPIO(P, 3) GPIO_ACTIVE_LOW>;
nvidia,dsi-te-gpio = <&tegra_aon_gpio TEGRA_AON_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
//nvidia,panel-bl-en-gpio = <&tegra_aon_gpio TEGRA_AON_GPIO(U, 3) GPIO_ACTIVE_HIGH>;
//nvidia,panel-bl-pwm-gpio = <&tegra_aon_gpio TEGRA_AON_GPIO(U, 5) GPIO_ACTIVE_HIGH>;
nvidia,dsi-instance = <DSI_INSTANCE_0>;
nvidia,dsi-n-data-lanes = <4>;
nvidia,dsi-pixel-format = <TEGRA_DSI_PIXEL_FORMAT_24BIT_P>;
nvidia,dsi-refresh-rate = <60>;
nvidia,dsi-video-data-type = <TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE>;
nvidia,dsi-video-clock-mode = <TEGRA_DSI_VIDEO_CLOCK_TX_ONLY>;
nvidia,dsi-video-burst-mode = <TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END>;
nvidia,dsi-virtual-channel = <TEGRA_DSI_VIRTUAL_CHANNEL_0>;
nvidia,dsi-panel-reset = <TEGRA_DSI_ENABLE>;
nvidia,dsi-power-saving-suspend = <TEGRA_DSI_DISABLE>;
nvidia,dsi-ulpm-not-support = <TEGRA_DSI_ENABLE>;
nvidia,dsi-init-cmd =
<TEGRA_DSI_GPIO_SET 1>,
<TEGRA_DSI_DELAY_MS 10>,
<TEGRA_DSI_GPIO_SET 0>,
<TEGRA_DSI_DELAY_MS 10>,
<TEGRA_DSI_GPIO_SET 1>,
<TEGRA_DSI_DELAY_MS 10>,
<0x0 DSI_DCS_WRITE_0_PARAM DSI_DCS_SET_TEARING_EFFECT_ON 0x00 0x00>,
<TEGRA_DSI_DELAY_MS 10>,
<0x0 DSI_DCS_WRITE_0_PARAM DSI_DCS_EXIT_SLEEP_MODE 0x0 0x0>,
<TEGRA_DSI_DELAY_MS 120>,
<0x0 DSI_DCS_WRITE_0_PARAM DSI_DCS_SET_DISPLAY_ON 0x0 0x0>,
<TEGRA_DSI_DELAY_MS 5>,
<TEGRA_DSI_SEND_FRAME 2>;
nvidia,dsi-n-init-cmd = <13>;
nvidia,dsi-suspend-cmd = <0x0 DSI_DCS_WRITE_0_PARAM DSI_DCS_SET_DISPLAY_OFF 0x0 0x0>,
<0x0 DSI_DCS_WRITE_0_PARAM DSI_DCS_ENTER_SLEEP_MODE 0x0 0x0>,
<TEGRA_DSI_DELAY_MS 80>;
nvidia,dsi-n-suspend-cmd = <3>;
disp-default-out {
nvidia,out-type = <TEGRA_DC_OUT_DSI>;
nvidia,out-width = <71>;
nvidia,out-height = <71>;
nvidia,out-flags = <TEGRA_DC_OUT_CONTINUOUS_MODE>;
nvidia,out-parent-clk = “pll_d”;
nvidia,out-xres = <720>;
nvidia,out-yres = <720>;
nvidia,out-align = <TEGRA_DC_ALIGN_LSB>;
nvidia,out-order = <TEGRA_DC_ORDER_RED_BLUE>;
};
display-timings {
720x720-60 {
clock-frequency = <34600000>;
hactive = <720>;
vactive = <720>;
hfront-porch = <10>;
hback-porch = <20>;
hsync-len = <20>;
vfront-porch = <10>;
vback-porch = <9>;
vsync-len = <10>;
nvidia,h-ref-to-sync = <0>;
nvidia,v-ref-to-sync = <0>;
};
};

Xrandr output:

Screen 0: minimum 8 x 8, current 4560 x 2160, maximum 32767 x 32767
DSI-0 connected 720x720+3840+1440 inverted (normal left inverted right x axis y axis) 0mm x 0mm
720x720 59.99*+

fbset output:

mode “720x720-60”
# D: 34.601 MHz, H: 44.936 kHz, V: 59.995 Hz
geometry 720 720 720 720 32
timings 28901 20 10 9 10 20 10
hsync high
vsync high
rgba 8/16,8/8,8/0,8/24
endmode

kernel dmesg output snippet (I had recompiled of_dc.c with the debug macro enabled):

[ 1.165981] tegradc 15200000.nvdisplay: disp0 connected to head0->/host1x/dsi
[ 1.166023] OF_DC_LOG: fb bpp 32
[ 1.166029] tegra_cec 3960000.tegra_cec: Enable clock result: 0.
[ 1.166038] OF_DC_LOG: fb flip on probe
[ 1.166046] OF_DC_LOG: dsi controller vs DSI_VS_1
[ 1.166052] tegra_cec 3960000.tegra_cec: tegra_cec_init started
[ 1.166056] OF_DC_LOG: Enable hs clock in lp mode 1
[ 1.166066] OF_DC_LOG: n data lanes 4
[ 1.166072] OF_DC_LOG: dsi video NONE_BURST_MODE_WITH_SYNC_END
[ 1.166078] OF_DC_LOG: dsi pixel format 24BIT_P
[ 1.166083] OF_DC_LOG: dsi refresh rate 60
[ 1.166089] OF_DC_LOG: dsi virtual channel 0
[ 1.166093] OF_DC_LOG: dsi instance 0
[ 1.166100] OF_DC_LOG: dsi panel reset 1
[ 1.166159] OF_DC_LOG: dsi te_gpio 265
[ 1.166165] OF_DC_LOG: dsi power saving suspend 0
[ 1.166170] OF_DC_LOG: dsi ulpm_not_supported 1
[ 1.166175] OF_DC_LOG: dsi video type VIDEO_MODE
[ 1.166207] OF_DC_LOG: dsi video clock mode TX_ONLY
[ 1.166212] OF_DC_LOG: dsi n_init_cmd 13
[ 1.166223] OF_DC_LOG: dsi n_suspend_cmd 3
[ 1.166257] OF_DC_LOG: boardinfo platform_boardid = 0 platform_boardversion = 0 display_boardid = 0 display_boardversion = 0
[ 1.166269] OF_DC_LOG: dc flag 1
[ 1.166275] OF_DC_LOG: out_width 71
[ 1.166279] OF_DC_LOG: out_height 71
[ 1.166291] tegradc 15200000.nvdisplay: No hpd-gpio in DT
[ 1.166300] OF_DC_LOG: default_out flag 0
[ 1.166304] OF_DC_LOG: tegra dc align lsb
[ 1.166309] OF_DC_LOG: tegra order red to blue
[ 1.166315] OF_DC_LOG: parent clk pll_d
[ 1.166320] OF_DC_LOG: framebuffer xres 720
[ 1.166325] OF_DC_LOG: framebuffer yres 720
[ 1.166340] OF_DC_LOG: of pclk 34600000
[ 1.166352] OF_DC_LOG: fb window Index 0
[ 1.166356] OF_DC_LOG: win mask 0x7
[ 1.166362] OF_DC_LOG: cmu enable 1
[ 1.166367] tegradc 15200000.nvdisplay: DT parsed successfully
[ 1.166394] tegradc 15200000.nvdisplay: Display dc.ffffff800b690000 registered with id=0
[ 1.166727] tegra_cec 3960000.tegra_cec: cec_add_sysfs ret=0
[ 1.166734] tegra_cec 3960000.tegra_cec: probed
[ 1.176807] tegra_nvdisp_bandwidth_register_max_config: max config iso bw = 16727000 KB/s
[ 1.176816] tegra_nvdisp_bandwidth_register_max_config: max config EMC floor = 665600000 Hz
[ 1.176821] tegra_nvdisp_bandwidth_register_max_config: max config hubclk = 357620000 Hz
[ 1.177139] tegradc 15200000.nvdisplay: vblank syncpt # 8 for dc 0
[ 1.177150] tegradc 15200000.nvdisplay: vpulse3 syncpt # 9 for dc 0
[ 1.180967] tegradc 15200000.nvdisplay: Force clock continuous mode
[ 1.183608] tegradc 15200000.nvdisplay: probed
…
[ 1.250327] tegradc 15200000.nvdisplay: dsi: ClkPost mipi range violated
[ 1.263461] tegradc 15200000.nvdisplay: dsi: ClkPost mipi range violated
[ 1.526380] tegradc 15200000.nvdisplay: dsi: ClkPost mipi range violated
[ 1.596375] tegradc 15200000.nvdisplay: dsi: video fifo overflow. Resetting flag
[ 1.605537] tegradc 15200000.nvdisplay: dsi: ClkPost mipi range violated
[ 1.614446] tegradc 15200000.nvdisplay: dsi: ClkPost mipi range violated

3

Hi,

For the “force clock continuous mode”, could you check whether nvidia,enable-hs-clk-in-lp-mode is being set to 1?

You could check the node under /proc/devicetree/host1x/dsi.

4

Hi Wayne,

I checked via dtc -I fs /proc/device-tree | grep nvidia,enable- and yes, it is being set to 1.

5

Please disable it to bypass the error “force clock continuous mode”.

6

I was able to disable it and no longer see the error message “force clock continuous mode”, so thanks for that. However, the contents shown on the dsi display remain the same as shown in my first post.

Is there another step I can try?

7

For such issue, you have to check the driver and see why “[ 1.250327] tegradc 15200000.nvdisplay: dsi: ClkPost mipi range violated” is happened.