DSI support on TX2

We are currently trying to get DSI to work with a custom panel on the jetson TX2. The panel DTS file is based off panel-s-wuxga-8-0.dtsi with our init and panel info added. With the TX1 this works correctly and the panel comes on. On the TX2 there is a FIFO underflow error.

Poking around in the C code in the file common.c at $KERNEL_SRC/kernel/kernel-4.4/drivers/soc/tegra/common.c
in the function tegra_get_fb_resource which gets the tegra_bootloader_fb start and size passed from cboot.

Adding debug code in this it seems that the HDMI display controller gets a valid fb from cboot yet the DSI controller has a null start and size regardless of which controller is allocated to DSI, 0, 1, or 2.

On the TX1, the same function returns a valid start and size for the DSI display controller.

Looking at the available cboot source file for the TX2 I found the following line in the code that creates this allocation.
$CBOOT_SRC/bootloader/partner/common/drivers/display/platform_data/tegrabl_display_dtb.c

if (du_type == DISPLAY_OUT_DSI) {
		pr_error("dsi not supported yet\n");
		err = TEGRABL_ERROR(TEGRABL_ERR_NOT_SUPPORTED, 0);
		goto fail_parse;

greping the cboot.bin for both the TX1 and TX2 shows this string is present in the TX2 binary but not in the TX1 binary which might explain why this issue is on the TX2 while the display works without issue on TX2.

How can I go about enabling the panel on the TX2 to make our panel work like on the TX1?

Hi anthony.l.speake,

Do you see the error message when fails to bring up your DSI panel on TX2?

The panel does come up on the TX2 but the display only works for about half a second where you can move the mouse around on a black screen. after which it freezes the image and no longer displays frames.

During this time the following message appears multiple times on the console,

tegradc 15200000.nvdisplay: dsi: video fifo underflow. Resetting flag

The error message from cboot on TX2 is always the same showing,

[0001.959] E> dsi not supported yet

which is troubling since all documentation I have read up to this point along with TX2 DSI forum posts here indicate that DSI is supported.

Is nvidia looking into this issue?

I saw this post while debugging the same issue on my hardware. I saw both of the messages that you see.

It’s true that cboot doesn’t support DSI, but that’s OK for me as I only need to use it in Linux and the splash is displayed within a few seconds.

I saw video fifo underflow because my video timings were messed up. You need to make sure you have the right settings in device tree for dsi-pkt-seq. In my case, I tried driving my panel with settings corresponding to non-burst mode with sync pulses, but that meant that I ended up with a negative number for the length of the HSA packet (my HSYNC is 2 pixels). I actually needed non-burst mode with sync events (that is the start of sync pulses is indicated but not the end).

The Parker TRM has some pictures and equations in section 24.8.2.2 that help with creating these.

Here is a snippet of my panel .dtsi with the correct dsi-pkt-seq for non-burst mode with sync events:
nvidia,dsi-pkt-seq =
/Blanking line with Vsync/
<CMD_VS LEN_SHORT PKT_LP LINE_STOP>,
/End of Vsync line/
<CMD_HS LEN_SHORT PKT_LP LINE_STOP>,
/Blanking line/
<CMD_HS LEN_SHORT PKT_LP LINE_STOP>,
/Active line/
<CMD_HS LEN_SHORT CMD_BLNK LEN_HBP CMD_RGB_24BPP LEN_HACTIVE3 CMD_BLNK LEN_HFP LINE_STOP>,
/First blank line after active/
<CMD_HS LEN_SHORT PKT_LP LINE_STOP>,
/First Active line after blank/
<CMD_HS LEN_SHORT CMD_BLNK LEN_HBP CMD_RGB_24BPP LEN_HACTIVE3 CMD_BLNK LEN_HFP LINE_STOP>;
nvidia,dsi-video-burst-mode = <TEGRA_DSI_VIDEO_NONE_BURST_MODE>;

I hope that helps!

Also, another handy check is to read the DSI controller registers at:
/sys/kernel/debug/tegra_dsi/regs

You can verify that you have the right packet lengths by looking at DSI_PKT_LEN__

We are looking into this fix however we have not made any progress in getting the DSI to work.

We managed to fix the underflow issue and get one display to turn on. The problem was the SOL_DELAY was to short in the dsi.c. increasing the delay removed the underflow and allowed for the display to turn on.

line 1497 in tegra_dsi_set_sol_delay was changed from

sol_delay = VIDEO_FIFO_LATENCY_PIXEL_CLK *
				dsi->pixel_scaler_mul / dsi->pixel_scaler_div;

to the following

dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz + dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
			dsi_to_pixel_clk_ratio *= 1000/8;
			sol_delay = ((VIDEO_FIFO_LATENCY_PIXEL_CLK + 14) * dsi_to_pixel_clk_ratio) *
							dsi->pixel_scaler_mul / (dsi->pixel_scaler_div * dsi->info.n_data_lanes);